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1364 Commits

Author SHA1 Message Date
Michael Walle 10495e72d0 lm32: rename mem array in lm32_dp_ram 
Be compatible with original proprietary DP RAM instantiation. This is
needed for simulation, where r0 is initialized to zero in lm32_cpu.v.

Signed-off-by: Michael Walle <michael@walle.cc>
 2012-11-14 14:08:06 +01:00
Michael Walle 47baad4fe1 lm32: replace clogb2 by builtin $clog2 
This function is fixed in ISE since version 14.1 (see AR #44586). If the
builtin function is used, the design can be simulated with Icarus Verilog.

Signed-off-by: Michael Walle <michael@walle.cc>
 2012-11-14 14:07:28 +01:00
Sebastien Bourdeauducq ced98d7bee framebuffer: use new SingleGenerator 2012-10-09 21:11:26 +02:00
Sebastien Bourdeauducq dd6eacba62 Remove uses of the RE signal on field registers 2012-10-09 19:08:37 +02:00
Florent Kermarrec f96a28fc32 start MigLa Doc 2012-09-26 23:05:38 +02:00
Florent Kermarrec 6aeb69b329 update schematics 2012-09-18 23:09:21 +02:00
Florent Kermarrec 7b7ef4f8dc update doc 2012-09-18 16:21:32 +02:00
Florent Kermarrec 4864e08b88 add Setup.py / .gitignore 
start documentation
 2012-09-18 00:22:52 +02:00
Florent Kermarrec b5980a90cc add test_MigLa_1 example : csr access analyzing 2012-09-17 20:15:35 +02:00
Florent Kermarrec 0be7704a85 -add mask on Term 2012-09-17 18:37:23 +02:00
Florent Kermarrec 62bede5eef improve truthtable tool 2012-09-17 17:27:50 +02:00
Florent Kermarrec eba6a2c764 new MigLa Class, simplify & clean up 2012-09-17 17:00:47 +02:00
Florent Kermarrec dbc208395d use of new migen clock_domains convention 2012-09-17 15:27:37 +02:00
Florent Kermarrec a7658cdc6c update README 2012-09-16 11:51:03 +02:00
Florent Kermarrec d97a640b53 add ramp / square / sinus signal generation in examples 2012-09-16 11:49:16 +02:00
Florent Kermarrec 5e84b12980 simplify recorder 2012-09-16 11:48:32 +02:00
Florent Kermarrec d21099f764 examples/de1 : add ramp / square mode 2012-09-15 22:29:50 +02:00
Florent Kermarrec 88d5a593ef fix bug put_ptr on start, separate put / get processes 2012-09-15 20:22:02 +02:00
Florent Kermarrec 50da5bfbf0 remove buggy workaround on read 2012-09-15 20:13:18 +02:00
Florent Kermarrec 84fabd28a2 fixes & clean up 2012-09-15 00:57:52 +02:00
Florent Kermarrec 5b0a8a798f add test_MigLa.py (Wip) 
fixes
 2012-09-14 14:08:20 +02:00
Florent Kermarrec 79af96c190 add access methods 2012-09-14 12:57:09 +02:00
Florent Kermarrec cde176a0b7 migScope/tools/truthtable.py: add function to remove duplicate operands 2012-09-14 12:26:48 +02:00
Florent Kermarrec aac16a9e11 add test_MigIo.py for de0_nano and de1 example 2012-09-13 13:18:03 +02:00
Florent Kermarrec 619671ad73 fix write function 2012-09-13 13:15:05 +02:00
Florent Kermarrec 8e86be1a6a add address parameter to migIo 2012-09-13 13:14:27 +02:00
Florent Kermarrec f4369c917f add spi2Csr tools : Python Host & Arduino Uart<-->Spi bridge 2012-09-13 11:34:19 +02:00
Florent Kermarrec c7e2b0c43e examples/de1: use of MigIo 2012-09-12 22:20:07 +02:00
Florent Kermarrec fc6225273b add MigIo Class 2012-09-12 22:19:42 +02:00
Florent Kermarrec bb6045e279 update README 2012-09-12 18:09:12 +02:00
Florent Kermarrec af64beec53 examples/de1: fix top 2012-09-12 18:07:36 +02:00
Florent Kermarrec fb624fddc4 initialize de1 example 2012-09-12 17:56:36 +02:00
Florent Kermarrec 24b7ba8722 examples/de0_nano : add load cmd / change rst polarity 2012-09-12 16:53:08 +02:00
Sebastien Bourdeauducq c86dd3cbef Define clock domains instead of passing extra clocks as regular signals 2012-09-11 00:21:07 +02:00
Sebastien Bourdeauducq 5931c5eb59 Basic support for new clock domain and instance API 2012-09-10 23:47:06 +02:00
Florent Kermarrec 4a59b63151 Clean up 2012-09-09 23:46:26 +02:00
Florent Kermarrec 7a24ee7027 Wip de0_nano example 2012-09-09 23:27:51 +02:00
Florent Kermarrec 6b8dda03c6 Wip de0_nano example 2012-09-09 22:32:09 +02:00
Florent Kermarrec 1578c74895 Initialize de0_nano example 2012-09-09 21:18:09 +02:00
Florent Kermarrec b8eaf0906a Clean up 2012-09-09 20:51:15 +02:00
Florent Kermarrec 2092c5a138 add global tb, fix bugs 2012-09-09 20:38:01 +02:00
Florent Kermarrec 289d35b952 simplify registers mgnt 2012-09-09 14:37:55 +02:00
Florent Kermarrec 2abd7f664d add tb_RecorderCsr.py 
fixs in recorder.py
 2012-08-27 00:44:26 +02:00
Florent Kermarrec d34c877401 split migScope to trigger & recorder 2012-08-26 21:30:23 +02:00
Florent Kermarrec a99a902fef add vcd generator 2012-08-26 20:56:56 +02:00
Florent Kermarrec 97cca81e0c tb_TriggerCsr.py : use truth table generator for Sum Lut 2012-08-26 15:44:43 +02:00
Florent Kermarrec 68750445cd add truth table generator 2012-08-26 15:15:44 +02:00
Florent Kermarrec bf7864104a tb_spi2Csr: Add clk_ratio 
tb_spi2Csr: Add Read
spi2Csr : fixs
 2012-08-26 13:03:11 +02:00
Florent Kermarrec 2e54001fc1 - fix Spi2Csr mistakes 2012-08-25 23:29:23 +02:00
Florent Kermarrec b5a44f2e98 add sim: tb_Spi2Csr.py (skeleton, WIP) 2012-08-25 21:53:06 +02:00