Florent Kermarrec
|
492a5acfe3
|
add Run Length Encoding
|
2013-03-23 22:06:08 +01:00 |
Sebastien Bourdeauducq
|
e06585d9fe
|
dvisampler: clean up EDID data
|
2013-03-23 13:48:40 +01:00 |
|
Florent Kermarrec
|
eeab7051be
|
remove doc (to be re-written)
|
2013-03-23 12:28:18 +01:00 |
|
Florent Kermarrec
|
88748bd74f
|
simplify recorder
|
2013-03-23 12:26:22 +01:00 |
|
Sebastien Bourdeauducq
|
34b8388b45
|
dvisampler: decode before channel sync
|
2013-03-22 23:49:25 +01:00 |
|
Sebastien Bourdeauducq
|
037625886d
|
dvisampler: decoding
|
2013-03-22 21:28:17 +01:00 |
|
Sebastien Bourdeauducq
|
d65941d6cc
|
dvisampler: channel synchronization
|
2013-03-22 18:37:10 +01:00 |
|
Florent Kermarrec
|
99a78b8e33
|
clean up
|
2013-03-22 14:01:38 +01:00 |
|
Florent Kermarrec
|
5e48f9c005
|
update driver api
|
2013-03-22 12:35:12 +01:00 |
|
Florent Kermarrec
|
b1cbfe2326
|
clean up/fixes
|
2013-03-22 11:31:21 +01:00 |
|
Sebastien Bourdeauducq
|
515cdb2bd8
|
dvisampler: character synchronization
|
2013-03-21 22:56:13 +01:00 |
|
Sebastien Bourdeauducq
|
7c4ca4fd66
|
dvisampler/datacapture: deserialize to 10 bits
|
2013-03-21 19:06:15 +01:00 |
|
Sebastien Bourdeauducq
|
fa2331e084
|
dvisampler/clocking: generate pix reset
|
2013-03-21 19:02:04 +01:00 |
|
Sebastien Bourdeauducq
|
2315544b36
|
software/videomixer: quick hack for phase detection
|
2013-03-21 15:32:26 +01:00 |
|
Florent Kermarrec
|
db1ceccca1
|
fix uart2Csr and update miio example
|
2013-03-21 12:18:04 +01:00 |
|
Sebastien Bourdeauducq
|
a6a3d93059
|
software: add videomixer base files
|
2013-03-21 10:42:31 +01:00 |
|
Sebastien Bourdeauducq
|
bb566c9e7c
|
software/bios: change boot order
|
2013-03-21 10:41:56 +01:00 |
|
Sebastien Bourdeauducq
|
0a14c3714b
|
dvisampler: software controlled phase detector
|
2013-03-21 00:46:29 +01:00 |
|
Florent Kermarrec
|
24211574ec
|
update de0nano example/ remove de1 (wip)
|
2013-03-18 23:03:52 +01:00 |
|
Florent Kermarrec
|
36f3556028
|
Add uart2csr
|
2013-03-18 21:45:07 +01:00 |
|
Sebastien Bourdeauducq
|
28cb97068c
|
dvisampler/clocking: proper pix5x reset synchronization
|
2013-03-18 20:31:59 +01:00 |
|
Sebastien Bourdeauducq
|
5126f616fb
|
dvisampler: use pix5x as IODELAY clock
|
2013-03-18 19:03:17 +01:00 |
|
Sebastien Bourdeauducq
|
48aae9bee5
|
Use Instance.Input(..., ClockSignal/ResetSignal) instead of Instance.ClockPort/ResetPort
|
2013-03-18 17:44:01 +01:00 |
|
Sebastien Bourdeauducq
|
0c0140a8fb
|
m1crg: set CLKIN_PERIOD for vga_clock_gen
|
2013-03-17 20:16:58 +01:00 |
|
Sebastien Bourdeauducq
|
74cc045ee1
|
dvisampler/datacapture: connect IODELAY IOCLK0
|
2013-03-17 17:42:22 +01:00 |
|
Sebastien Bourdeauducq
|
621526fb7d
|
dvisampler/datacapture: fix tap counter reg
|
2013-03-17 17:36:49 +01:00 |
|
Sebastien Bourdeauducq
|
3a0cf278fd
|
dvisampler: fixes
|
2013-03-17 15:41:50 +01:00 |
|
Sebastien Bourdeauducq
|
9f02ced39e
|
dvisampler: add clocking and phase detector
|
2013-03-17 14:43:10 +01:00 |
|
Sebastien Bourdeauducq
|
0168f83523
|
MultiReg: remove idomain
|
2013-03-15 19:51:29 +01:00 |
|
Sebastien Bourdeauducq
|
b2173bba9f
|
Use new ClockDomain API
|
2013-03-15 19:17:05 +01:00 |
|
Sebastien Bourdeauducq
|
2ae504fb9b
|
software/bios: default length 4 for mr command
|
2013-03-13 19:59:39 +01:00 |
|
Sebastien Bourdeauducq
|
eaef3464e9
|
Instantiate DVI sampler core for both ports
|
2013-03-13 19:56:56 +01:00 |
|
Sebastien Bourdeauducq
|
e99bafe52b
|
dvisampler: add core, EDID support
|
2013-03-13 19:56:26 +01:00 |
|
Sebastien Bourdeauducq
|
1e7783a41e
|
build.py: use implicit get_fragment
|
2013-03-12 16:13:20 +01:00 |
|
Sebastien Bourdeauducq
|
a23df42a7a
|
Use automatic register naming
|
2013-03-12 15:47:54 +01:00 |
|
Florent Kermarrec
|
60e2cdfe79
|
get_registers --> get_registers_glue since it's conflicting with new Migen register automatic detection
|
2013-03-11 20:05:30 +01:00 |
|
Sebastien Bourdeauducq
|
a9b723568a
|
Use new module, autoreg and eventmanager Migen APIs
|
2013-03-10 19:32:38 +01:00 |
|
Sebastien Bourdeauducq
|
2059592db2
|
software/libcompiler-rt: add ctzsi2
|
2013-03-06 11:10:16 +01:00 |
|
Florent Kermarrec
|
edce543b14
|
adapt to migen changes
|
2013-03-01 01:09:00 +01:00 |
|
Florent Kermarrec
|
80e9db7e61
|
use mibuild for de1 example
|
2013-02-28 23:11:41 +01:00 |
|
Florent Kermarrec
|
58a6acba27
|
use mibuild for de0_nano example
|
2013-02-28 23:02:06 +01:00 |
|
Florent Kermarrec
|
58edd7632c
|
compiles but untested
|
2013-02-28 00:32:42 +01:00 |
|
Florent Kermarrec
|
5accd48a17
|
doc: update
|
2013-02-26 23:45:01 +01:00 |
|
Florent Kermarrec
|
87336128a3
|
sim: update
|
2013-02-26 23:25:10 +01:00 |
|
Florent Kermarrec
|
ae900c9c16
|
examples: use miscope.bridges
|
2013-02-26 23:20:29 +01:00 |
|
Florent Kermarrec
|
5fc89f0c71
|
move spi2csr to briges/spi2csr
|
2013-02-26 23:17:34 +01:00 |
|
Florent Kermarrec
|
f823d06cf1
|
examples: update & simplify
|
2013-02-26 23:14:09 +01:00 |
|
Florent Kermarrec
|
b3ae31ee2f
|
examples/../top: update
|
2013-02-26 23:00:37 +01:00 |
|
Sebastien Bourdeauducq
|
356416fcdc
|
lm32: update
|
2013-02-24 17:42:28 +01:00 |
|
Sebastien Bourdeauducq
|
70f4c74d46
|
m1crg: advance off-chip DDR clock phase
|
2013-02-24 17:41:56 +01:00 |