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1364 Commits

Author SHA1 Message Date
Florent Kermarrec 8e67d6e69f liteeth: fix example design generation and remove VivadoProgrammer from platfom. (TODO: remove others duplicates) 2015-02-28 11:08:17 +01:00
Florent Kermarrec 2c3e8a2804 liteeth: fix example design generation and remove VivadoProgrammer from platfom. (TODO: remove others duplicates) 2015-02-28 11:04:48 +01:00
Florent Kermarrec 0dfca49e68 litesata: move file and modify import to misoclib.mem.litesata 2015-02-28 11:03:24 +01:00
Florent Kermarrec b6358be0a1 merge litesata 2015-02-28 10:48:08 +01:00
Florent Kermarrec df0ba1b03c litescope: create example_designs directory 2015-02-28 10:42:12 +01:00
Florent Kermarrec c4ebf244a1 litescope: move files and modify import to misoclib.tools.litescope 2015-02-28 10:33:46 +01:00
Florent Kermarrec b274e948dc merge litescope 2015-02-28 10:24:49 +01:00
Florent Kermarrec a43c555ee3 misoclib/com: add spi (only SPIMaster for now) 2015-02-28 09:43:03 +01:00
Florent Kermarrec 2c51adcd68 misoclib: better organization (create cores categories: cpu, mem, com, ...) 2015-02-28 09:40:44 +01:00
Florent Kermarrec 6b93849a08 gensoc: parameter check is now more restrictive, add additional info to help user 2015-02-28 03:12:00 +01:00
Florent Kermarrec 8e04ef7b95 test minicon with de0nano (OK) and fix missing self in gensoc 2015-02-27 20:00:16 +01:00
Florent Kermarrec f1200d6388 gensoc: move I/O for rom initialization to make.py 2015-02-27 19:48:07 +01:00
Florent Kermarrec 074f576340 targets: add de0nano (100MHz, integrated bios and SDRAM) 2015-02-27 19:47:32 +01:00
Florent Kermarrec cb38580400 make.py fix indent 2015-02-27 18:58:36 +01:00
Florent Kermarrec 5e2e9338d2 bios: we can now use -Ot with_rom True on targets to force bios implementation in integrated rom (can speed up debug we don't want to reflash SPI or NOR flash) 2015-02-27 17:22:44 +01:00
Florent Kermarrec b031c5edae targets: fix MiniSoC 2015-02-27 17:12:37 +01:00
Florent Kermarrec e07e124118 sdram: import dfi, lasmibus, wishbone2lasmi from Migen in sdram/bus dir 
We will maybe move things, but at least it's in MiSoC now
 2015-02-27 17:07:44 +01:00
Florent Kermarrec 07b9cabd0d gensoc: make it more generic (a SoC does not necessarily have a CPU) 2015-02-27 16:39:00 +01:00
Florent Kermarrec 367db268ad reserve csr_map 0-->16 for gensoc internal csrs 2015-02-27 14:18:13 +01:00
Florent Kermarrec be0eb8d265 use cachesize reported in wishbone2lasmi 2015-02-27 14:13:38 +01:00
Florent Kermarrec 9814001c79 create cpu dir and move lm32/mor1kx in it 2015-02-27 10:51:03 +01:00
Florent Kermarrec 9f636f7985 move memtest to sdram 2015-02-27 10:47:54 +01:00
Florent Kermarrec b817cf49b3 replace self._r_register by self._register in all CSR declaration 2015-02-27 10:36:09 +01:00
Florent Kermarrec e4de5a0c9d make.py: avoid some actions in make all (do not flash if load-bitstream is specified or if bios is in blockram) 2015-02-27 10:23:17 +01:00
Florent Kermarrec 77a6f580e2 gensoc: add check_cpu_memory_region and check_csr_region to detect csr and mem regions conflicts 2015-02-27 10:23:02 +01:00
Florent Kermarrec 617bc70d7f liteeth: move doc 2015-02-27 09:15:54 +01:00
Robert Jordens 2b12679ef6 add pipistrello target 2015-02-26 21:35:42 -07:00
Robert Jordens c9ed38dec8 gensoc: missing self. 2015-02-26 21:32:11 -07:00
Sebastien Bourdeauducq a3909bb5e2 Merge branch 'master' of https://github.com/m-labs/misoc 2015-02-26 21:28:12 -07:00
Yann Sionneau 8364fe6674 target/kc705: allow access to pll_sys signal before BUFG 2015-02-26 15:56:10 -07:00
Florent Kermarrec 09fbbca53e gensoc: cpus now directly add their verilog sources 2015-02-26 20:49:21 +01:00
Florent Kermarrec 5e8a0c496d gensoc: add mem_map and mem_decoder to avoid duplications 2015-02-26 20:12:27 +01:00
Florent Kermarrec 5ac5ffe359 gensoc: get platform_id from platform 2015-02-26 19:07:19 +01:00
Florent Kermarrec 554731ae44 targets/simple: make it generic (no default_platform, use platform's default_clk_name/default_clk_period) 2015-02-26 13:08:15 +01:00
Florent Kermarrec 02b3f51382 liteeth: fix example_designs generation 2015-02-26 10:23:38 +01:00
Florent Kermarrec 00862a383c liteeth: fix import (from liteeth --> from misoclib.liteeth) 2015-02-26 09:48:37 +01:00
Florent Kermarrec 60effe1d95 move files to liteeeth and create example_designs directory 2015-02-26 09:35:14 +01:00
Sebastien Bourdeauducq 0267868cbe remove litex submodule 2015-02-25 10:40:44 -07:00
Sebastien Bourdeauducq 658cb0e405 merge liteeth 2015-02-25 10:35:39 -07:00
Sebastien Bourdeauducq 8015d12692 move files for misoc integration 2015-02-25 10:34:11 -07:00
Florent Kermarrec eef679b6d4 phy/sim: generate sop/eop 2015-02-25 17:47:44 +01:00
Florent Kermarrec a559fc77c8 remove upload optimization (we will use wishbone later for performance) 2015-02-24 18:01:04 +01:00
Florent Kermarrec 6b7026f521 add sim phy 2015-02-24 01:42:56 +01:00
Florent Kermarrec b6ebcece95 add read grouping to etherbone, we now have interesting upload speeds... :) 2015-02-23 18:58:31 +01:00
Florent Kermarrec ac5b7c073a test: add make.py to replace static config.py file 2015-02-23 18:55:19 +01:00
Florent Kermarrec 71f3a5bf13 prepare reads grouping to speed up upload 2015-02-23 18:11:08 +01:00
Florent Kermarrec e309ba55ea use new Migen sel signal to change the way we upload data (will enable fifo bursts) 2015-02-23 12:34:04 +01:00
Florent Kermarrec d3486dba91 rle: increase dw automatically when needed 2015-02-23 09:41:18 +01:00
Florent Kermarrec 2a2c3af380 host/dump: optimize get_bits / decode_rle since we can now have large dumps 2015-02-23 02:14:20 +01:00
Florent Kermarrec 861c54760e host/driver/reg: use burst mode to speed up upload of data (useful with Etherbone) 2015-02-23 00:49:59 +01:00