Florent Kermarrec
ed2578799b
test: add test_axi_lite (with test code from soc/interconnect/axi_lite lightly modified)
2019-02-27 22:24:56 +01:00
Florent Kermarrec
4aa07f2ae9
soc/interconnect: rename axi to axi_lite
2019-02-27 22:11:09 +01:00
Florent Kermarrec
6a4c133cd2
test: add basic test_csr
2019-02-27 21:46:00 +01:00
enjoy-digital
c9f9e237d9
Merge pull request #149 from daveshah1/versa_trellis
...
Add trellis build option to versa_ecp5 and bring trellis support up to date
2019-02-25 19:26:07 +01:00
David Shah
ff7e0fab6a
versa_ecp5: Add option to build with Trellis
2019-02-25 18:02:04 +00:00
David Shah
024b41c5b2
trellis: Add LPF frequency constraints and remove -nomux
2019-02-25 18:01:35 +00:00
Florent Kermarrec
e38dfd99e8
soc/software/sdram: fix compilation on ultrascale
2019-02-25 16:12:21 +01:00
Florent Kermarrec
5f29a12ee7
targets/versa_ecp5: integrate DDR3
2019-02-25 15:27:08 +01:00
Florent Kermarrec
3dd529e40b
soc/software/bios/sdram: add ECP5 support
2019-02-25 14:41:33 +01:00
Florent Kermarrec
2fd6d0e7e1
soc/software/bios/sdram: improve write_level robustness
2019-02-25 14:38:24 +01:00
Florent Kermarrec
36772b75f6
soc/software/bios/sdram: improve sdrlevel readibility
2019-02-25 14:37:31 +01:00
Florent Kermarrec
6a980781d3
soc/software/bios/sdram: add helpers for rst/inc of delays
2019-02-25 14:36:47 +01:00
enjoy-digital
dad7b292aa
Merge pull request #148 from daveshah1/versa_remove_n
...
versa_ecp5: Remove negative diff IO pins
2019-02-22 14:32:45 +01:00
David Shah
321dd8fcf6
versa_ecp5: Remove negative diff IO pins
...
In Lattice FPGAs only the positive side of differential pairs should
be specified (unlike Xilinx)
These are a warning on Diamond (which trims unused IO) and an error
with Yosys/nextpnr (which doesn't so they conflict when the positive
pin is 'expanded').
Already this is the case for the clock input, this commit performs
the same change for the DDR3 pins.
2019-02-22 12:12:10 +00:00
Florent Kermarrec
c03b1ad13a
platforms/versa_ecp5: add ddram pins
2019-02-20 22:45:19 +01:00
Florent Kermarrec
ff155a474d
soc/tools/remote/comm_uart: be sure to flush in waiting bytes before read and write
2019-02-16 00:08:24 +01:00
Florent Kermarrec
d3ecdd9995
soc/cores/clock: add actual clk_freqs to config
2019-02-14 10:41:27 +01:00
Florent Kermarrec
af52842fbb
soc_sdram: add use_full_memory_we parameter to allow disabling vivado workaround on small l2 caches
2019-02-12 12:12:40 +01:00
Florent Kermarrec
32543430c0
build/lattice/common/LatticeECXTrellisImpl: add support for nbits == 1
2019-02-11 19:41:12 +01:00
Florent Kermarrec
aabf042d38
soc_sdram: don't generate sdram initialization error message when integrated_main_ram is used
2019-02-11 09:23:39 +01:00
Florent Kermarrec
f51ad43607
build/lattice/common: add LatticeiCE40DDROutput
2019-02-07 16:23:55 +01:00
Florent Kermarrec
22ccf9ddf1
platforms/nexys_video: add LPC transceivers pins
2019-02-01 23:39:17 +01:00
Florent Kermarrec
1d9c55888f
build/sim: add jtagremote module (thanks LamdaConcept)
2019-01-30 14:01:19 +01:00
Florent Kermarrec
57b8bdd530
soc/integration/soc_core: allow disabling wishbone timeout
2019-01-29 12:47:11 +01:00
Florent Kermarrec
05dcb5cadc
soc/interconnect/wishbone: increase bus error timeout to 1e6 cycles
2019-01-27 08:28:01 +01:00
Florent Kermarrec
02708d3b0f
boards/platform/kc705: add sfp pins (both tx and rx)
2019-01-23 08:40:47 +01:00
Florent Kermarrec
8344a6a4ef
soc/cores/clock: add USIDELAYCTRL
2019-01-22 12:50:05 +01:00
Florent Kermarrec
7e0dd37616
soc/integration/soc_sdram: round port.data_width/l2_size to nearest power of 2 when it's not the case
...
With ECC configurations, native port data_width is not necessarily a power of 2.
2019-01-22 09:08:35 +01:00
Florent Kermarrec
871b958f85
boards/targets: improve presentation
2019-01-21 10:40:41 +01:00
Florent Kermarrec
a318343afb
boards/platforms/kcu105: add si570_refclk
2019-01-21 10:40:37 +01:00
Florent Kermarrec
48312890e5
boards/platforms/kc705: use vivado as default programmer
2019-01-21 10:40:32 +01:00
Florent Kermarrec
1b23890e0d
soc/cores/clock: allow ClockSignal to be used for clkin
2019-01-16 22:05:52 +01:00
Florent Kermarrec
387ee04130
build/sim/core: fix coverage
2019-01-11 15:01:58 +01:00
Florent Kermarrec
482abf9b43
build/sim/core: set -Wno-BLKANDNBLK (prevent blocking/non-blocking assigns on a same structure in system verilog)
2019-01-11 13:51:15 +01:00
Florent Kermarrec
9c5f654773
build/sim/core: set unroll-count to 256 to prevent Error-BLKLOOPINIT
2019-01-11 13:39:09 +01:00
Florent Kermarrec
f132012de1
build/sim: disable Warning-WIDTH
2019-01-10 16:03:09 +01:00
Florent Kermarrec
7c67bac723
soc/cores/cpu/vexriscv: set default variant to None in add_sources
2019-01-09 10:28:24 +01:00
Florent Kermarrec
648015d78e
soc/cores/cpu/vexriscv: move verilog variant selection to add_sources
2019-01-09 09:19:40 +01:00
Florent Kermarrec
2b5a6f1058
targets/kcu105: use USMMCM
2019-01-08 14:14:28 +01:00
Florent Kermarrec
86e19e6232
targets: pass speedgrade to S7PLL/S7MMCM
2019-01-08 13:50:12 +01:00
Florent Kermarrec
2581a00380
soc/cores/clock: add Xilinx Ultrascale PLL/MMCM
2019-01-08 13:21:53 +01:00
Florent Kermarrec
68e1dfca28
boards: avoid duplicating platforms that can be found in migen/litex-buildenv
...
The platforms that are kept are the ones used for litex development.
2019-01-06 19:01:19 +01:00
Florent Kermarrec
041bf41226
soc/integration/cpu_interface: generate name for Memories in get_csr_header
2019-01-05 10:57:37 +01:00
Florent Kermarrec
9f5d0cef6b
utils/litex_server: allow specify uart_baudrate as float
2019-01-03 10:38:14 +01:00
Florent Kermarrec
2c43f6f7dc
targets/ulx3s: use pll for phase shift, enable refresh, memtest ok
2018-12-28 15:58:28 +01:00
Florent Kermarrec
5ef4d09caa
targets/versa_ecp5: use pll for phase shift, enable refresh, memtest ok
2018-12-28 15:39:20 +01:00
Florent Kermarrec
9c801fbe50
soc/cores/clock/ECP5PLL: add basic phase support
2018-12-28 15:03:12 +01:00
Florent Kermarrec
a7b5b9d212
litex_sim: simplify, change sdram module and enable sdram refresh.
2018-12-27 20:36:50 +01:00
Florent Kermarrec
a7378a721c
.gitmodules: use our copy of tapcfg since https://github.com/nizox/tapcfg no longer exists.
2018-12-23 19:47:48 +01:00
Florent Kermarrec
2deffd8c8a
build/sim/verilator: compile sim just before running and not when building.
2018-12-21 09:59:34 +01:00
