Matthias Breithaupt
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ed510bb9df
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liblitespi: add 4k erase function
Signed-off-by: Matthias Breithaupt <m.breithaupt@vogl-electronic.com>
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2024-11-26 08:23:56 +01:00 |
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enjoy-digital
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10dcc73676
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Merge pull request #2125 from trabucayre/ecp5_diamond_tristate
build/lattice/common.py: added Tristate support for ECP5 when build with diamond
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2024-11-18 12:40:24 +01:00 |
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Florent Kermarrec
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52148c7aad
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soc/integration/soc_core: Fix with_uartbone changes.
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2024-11-18 11:07:51 +01:00 |
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Gwenhael Goavec-Merou
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211ce59df4
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build/lattice/common.py: added Tristate support for ECP5 when build with diamond
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2024-11-17 11:32:33 +01:00 |
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enjoy-digital
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8041969e00
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Merge pull request #2100 from VOGL-electronic/efinix_io_optimize
efinix: gpio: use constant output option
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2024-11-15 09:38:50 +01:00 |
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enjoy-digital
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8399c919bd
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Merge pull request #2122 from acceleratedtech/accelerated/uart-dynamic-baudrate-for-upstream
feat: add uart_with_dynamic_baudrate to SoCCore
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2024-11-15 09:36:20 +01:00 |
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enjoy-digital
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2b3fd723a2
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Merge pull request #2101 from VOGL-electronic/bios_spi_fix
bios: litespi: clear rx queue after write Beta
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2024-11-13 11:12:51 +01:00 |
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enjoy-digital
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0f45ea221e
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Merge pull request #2119 from long-pham/pr_useAllCPUCores
Utilizing all available CPU cores in the software make cmd
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2024-11-12 21:45:07 +01:00 |
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enjoy-digital
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e9e0140c74
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Merge pull request #2118 from long-pham/pr_openfpgaloader
Add FTDI serial number option to openfpgaloader
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2024-11-12 21:40:57 +01:00 |
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enjoy-digital
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8ece14849a
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Merge pull request #2117 from long-pham/main
Use MMCME4_ADV in USPMMCM to enable finer-grained clock output ctrl
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2024-11-12 21:40:25 +01:00 |
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enjoy-digital
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d7a8743f20
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Merge pull request #2123 from trabucayre/vhd2vconverter_libraries
build/vhd2v_converter.py: allows users to pass a list of libraries files to compile before convert HDL.
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2024-11-12 21:38:38 +01:00 |
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enjoy-digital
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f056f37c29
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Merge pull request #2120 from juiceRv/fix/veril-fst-trace
Fixes: Fix not close trace file when the sim is finished
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2024-11-12 21:37:09 +01:00 |
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Gwenhael Goavec-Merou
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f731b36c9b
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build/vhd2v_converter.py: allows users to pass a list of libraries files to compile before convert HDL.
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2024-11-09 07:55:18 +01:00 |
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Jamey Hicks
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f53178d712
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feat: add uart_with_dynamic_baudrate to SoCCore
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2024-11-08 18:49:01 -05:00 |
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Li.XiongHui
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5fa144ec3a
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Fixes: Fix no close trace file when the sim is finished
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2024-11-07 14:41:26 +08:00 |
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Long Pham
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9cc8bf9866
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Switch to using MMCME4_ADV in USPMMCM to enable finer-grained clock output control
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2024-11-06 13:48:56 -08:00 |
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enjoy-digital
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8b4949edcd
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Merge pull request #2115 from CKeilbar/soc-region-check-fix
Fix SOC region range check
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2024-11-06 22:29:05 +01:00 |
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Florent Kermarrec
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de9d3ab314
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soc/cores/cpu/urv: Add DataBusToWishbone and use it.
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2024-11-06 21:59:11 +01:00 |
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Florent Kermarrec
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2b3913982c
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soc/cores/cpu/urv: Add InstructionBusToWishbone and use it.
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2024-11-06 21:49:39 +01:00 |
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Long Pham
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d8e168a81f
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Enhance software build performance by utilizing all available CPU cores in the builder
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2024-11-06 11:35:28 -08:00 |
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Long Pham
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935326e66c
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Add FTDI serial number option to openfpgaloader, useful when multiple similar boards are connected for CI/CD
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2024-11-06 11:25:54 -08:00 |
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Florent Kermarrec
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1204cfda9d
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soc/cores/cpu/urv: Fix add_sources.
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2024-11-05 17:33:32 +01:00 |
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Florent Kermarrec
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20b0e98fe0
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cpu/urv: Fix Instruction Bus conversion to Wishbone and only keep it now that working.
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2024-11-05 17:19:13 +01:00 |
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Chris Keilbart
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e9613499ea
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Fix SOC region range check
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2024-11-04 12:01:29 -08:00 |
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Florent Kermarrec
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0170462fe8
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soc/cores/jtag: Fix/Test p_init/p_INIT workaround.
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2024-11-04 14:34:28 +01:00 |
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enjoy-digital
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3f3249cdf0
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Merge pull request #2113 from trabucayre/toolchain_diamond_sdc
litex/build/lattice/diamond, platform: allows users to add custom sdc files
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2024-11-04 12:53:48 +01:00 |
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Gwenhael Goavec-Merou
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47e8b0273f
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litex/build/lattice/diamond, platform: allows users to add custom sdc files
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2024-11-04 12:42:38 +01:00 |
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Florent Kermarrec
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175e63ac4c
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soc/cores/jtag: Add p_INIT/p_init workaround on ECP5JTAG to support Diamond and Trellis toolchains without manual changes.
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2024-11-04 12:40:39 +01:00 |
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Florent Kermarrec
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4368d5a9ed
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test/test_led: Comment out TestWS1812 test since seems broken, will need to be investigated/fixed.
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2024-10-28 21:51:42 +01:00 |
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Florent Kermarrec
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61ab30a739
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soc/cores/jtag: Revert p_INIT since not tested.
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2024-10-28 20:05:47 +01:00 |
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enjoy-digital
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10184ad325
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Merge pull request #2097 from trabucayre/build_diamond_addition
Build diamond addition
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2024-10-28 20:05:01 +01:00 |
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enjoy-digital
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23df960859
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Merge pull request #2102 from Dolu1990/vexiiriscv-macsg
Vexiiriscv update
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2024-10-28 20:03:06 +01:00 |
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enjoy-digital
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dd092863f8
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Merge branch 'master' into vexiiriscv-macsg
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2024-10-28 20:02:56 +01:00 |
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enjoy-digital
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18714dfca3
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Merge pull request #2104 from andelf/fix/ws2812-of-1-led
Fixes #2103: calculate memory depth for WS2812
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2024-10-28 19:53:25 +01:00 |
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Dolu1990
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59fc1caac4
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Merge pull request #2099 from VOGL-electronic/vexiiriscv_sbi
vexiiriscv: add options and conditions
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2024-10-25 14:26:02 +02:00 |
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Fin Maaß
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773fb34079
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vexiiriscv: have opensbi behind a option
this way opensbi things are only activated,
when a linux variant is used.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
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2024-10-25 13:40:20 +02:00 |
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Andelf
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8c7e510473
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Fixes #2103: calculate memory depth for WS2812
See-also: https://github.com/m-labs/migen/pull/295
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2024-10-25 11:48:57 +08:00 |
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Dolu1990
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24db36ced5
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Merge remote-tracking branch 'origin/master' into wuff
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2024-10-24 16:02:52 +02:00 |
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Dolu1990
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375940ad7d
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soc/core/vexiiriscv: add macsg support (dma based ethernet)
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2024-10-24 16:00:51 +02:00 |
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Fin Maaß
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d7bf75a75c
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bios: litespi: add newline to debug output
add newline to debug output
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
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2024-10-24 15:12:12 +02:00 |
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Fin Maaß
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63fa4fda85
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bios: litespi: clear rx queue after write
clear rx queue at the end of spiflash_master_write().
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
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2024-10-24 15:10:37 +02:00 |
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Fin Maaß
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54973eb9cb
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build: efinix: use constant output option
use constant output option, when the output is a `Constant`
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
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2024-10-23 14:12:30 +02:00 |
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Fin Maaß
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2d96e99494
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build: io: SDRTristate: move check
check wraped signals instead of before.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
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2024-10-23 11:18:57 +02:00 |
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Fin Maaß
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70f4a349e5
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efinix: ifacewriter: fix in output
fix in OUTPUT
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
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2024-10-23 11:10:16 +02:00 |
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Fin Maaß
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d6eec8e76d
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efinix: ifacewriter: gpio: share common code
share common code for INPUT, INOUT and OUTPUT.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
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2024-10-23 11:08:58 +02:00 |
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enjoy-digital
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c1225736a8
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Merge pull request #2098 from enjoy-digital/urv
Add initial uRV CPU support.
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2024-10-17 19:45:44 +02:00 |
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Florent Kermarrec
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5f463dba87
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CHANGES.md: Update.
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2024-10-17 17:45:50 +02:00 |
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Florent Kermarrec
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aab8912f5a
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soc/cores/cpu/urv: Move ROM init to builder and allow switching between classical ROM or ROM integrated in CPU.
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2024-10-17 17:44:40 +02:00 |
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Florent Kermarrec
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9449d25911
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soc/cores/cpu/urv: Able to boot LiteX BIOS with im bus connected to synchronous memory.
- Replace im bus wishbone adaptation with synchronous memory (for now and initial tests).
- Correctly handle dm bus wishbone adaptation (Added FIFO).
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2024-10-17 16:54:20 +02:00 |
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Florent Kermarrec
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edb56e73aa
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soc/cores/cpu: Add initial uRV CPU support (not yet working).
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2024-10-16 22:24:07 +02:00 |
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