Commit Graph

106 Commits

Author SHA1 Message Date
Florent Kermarrec 04017519c8 soc/interconnect/axi: add Wishbone2AXILite 2019-11-20 12:32:22 +01:00
Florent Kermarrec 4b073a440a test/test_axi: cosmetic 2019-11-20 11:22:39 +01:00
Florent Kermarrec 6059712794 test/test_packet: add randomness on ready output, fix corner-cases on Packetizer/Depacketizer 2019-11-16 14:39:18 +01:00
Florent Kermarrec 9642893371 test/test_packet: add randomness on valid input, fix corner-cases on Packetizer 2019-11-16 08:49:04 +01:00
Florent Kermarrec 33c4d961b5 test/test_packet: add 32/64/128-bit loopback tests (passing :)) 2019-11-15 11:37:52 +01:00
Florent Kermarrec 824faf9722 test/test_packet: prepare for testing dw > 8-bit 2019-11-15 11:32:42 +01:00
Florent Kermarrec 442e23d7fd test: add initial test_packet
Use a header with 8,16,32,64,128-bit fields and test a Packetizer/Depacketizer loopback with random field values, random packet data & length.
2019-11-15 10:29:50 +01:00
Florent Kermarrec 650df0ebc2 test/test_targets: skip Minerva test on Travis-CI, remove commented tests 2019-10-28 11:00:08 +01:00
Florent Kermarrec 41ad08e8ef soc/cores/icap: simplify ICAPBitstream (untested) 2019-10-01 21:30:14 +02:00
Florent Kermarrec 63a813af9c soc_core: fix cpu_type=None case and add test for it 2019-09-30 08:26:38 +02:00
Florent Kermarrec 241c3c642b test/test_targets: update cpu-type to mor1kx 2019-09-29 17:12:15 +02:00
Florent Kermarrec 8c080e5fb6 soc/interconnect/csr: add initial field support 2019-09-13 20:01:31 +02:00
Florent Kermarrec 41fe7cae0b core/spi: add minimal SPISlave 2019-08-29 09:46:20 +02:00
Florent Kermarrec 4990bf33c0 soc/core: simplify/cleanup HyperRAM core
- rename core to hyperbus.
- change layout (cs_n with variable length instead of cs0_n, cs1_n).
- use DifferentialOutput when differential clock is used.
- add test (python3 -m unittest test.test_hyperbus).

Usage example:
from litex.soc.cores.hyperbus import HyperRAM
self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
self.add_wb_slave(mem_decoder(self.mem_map["hyperram"]), self.hyperram.bus)
self.add_memory_region("hyperram", self.mem_map["hyperram"], 8*1024*1024)
2019-08-16 14:04:58 +02:00
Florent Kermarrec a7895e4982 test/test_axi: remove use of rand_wait, rename rand_level to random 2019-07-23 21:02:09 +02:00
Florent Kermarrec ea619e3afe cores/spi: rename add_control paramter to add_csr 2019-07-20 12:56:37 +02:00
Florent Kermarrec 769d15d433 cores/spi: move CSR control/status to add_control method, add loopback capability and simple xfer loopback test
Moving control/status registers to add_control method allow using SPIMaster directly with exposed signals.
Add loopback capability (mostly for simulation, but can be useful on hardware too).
2019-07-13 12:55:19 +02:00
Florent Kermarrec ee8fec10ff soc/cores: add ECC (Error Correcting Code)
Hamming codes with additional parity (SECDED):
- Single Error Correction
- Double Error Detection
2019-07-13 11:44:29 +02:00
Florent Kermarrec 4c18c991bc cores: add ICAP core (tested with reconfiguration commands) 2019-07-05 18:30:34 +02:00
Florent Kermarrec 6b82f23ce1 cores: add simple and minimal hardware SPI Master with CPOL=0, CPHA=0 and build time configurable data_width and frequency. 2019-07-05 15:50:58 +02:00
Florent Kermarrec 7cd5c0f39b cores: add bitbang class with minimal hardware for I2C/SPI software bit-banging 2019-07-05 14:26:10 +02:00
Florent Kermarrec dc03b7fab9 boards: community supported boards are now located at https://github.com/litex-hub/litex-boards 2019-06-24 12:05:02 +02:00
Florent Kermarrec c7f36ab08f test: add copyright header 2019-06-23 23:31:11 +02:00
Florent Kermarrec ab1f580470 test/test_axi: remove litex.gen.sim import (was only useful for debug) 2019-06-12 11:28:06 +02:00
Florent Kermarrec 38a2d89a25 test/test_code8b10b: add test_coding 2019-06-10 18:53:30 +02:00
Florent Kermarrec 8fdd5220b3 test/test_prbs: add PRBSGenerator/Checker tests 2019-06-10 16:19:23 +02:00
Florent Kermarrec 55ebcc00eb test/test_targets: add de10lite 2019-06-05 20:03:19 +02:00
Florent Kermarrec b300c32103 test/test_targets: add de2_115, de1soc 2019-06-02 19:22:09 +02:00
Florent Kermarrec 67159349d6 soc/interconnect: remove axi_lite
axi_lite code was defining AXI4Lite signals and doing a AXI4Lite bridge to the
CSR bus when LiteX was not having proper AXI support. LiteX now has  proper AXI
support and it also cover what axi_lite was doing: To create a AXILite to CSR
bus, user can create an AXILite2Wishbone bridge and then connect the CSR bus
directly to the wishbone bus as done in the others non-AXI SoC.
2019-05-11 09:12:20 +02:00
Florent Kermarrec 745d83a332 boards: add initial NeTV2 support (clocks, leds, dram, ethernet) 2019-05-10 18:55:40 +02:00
Florent Kermarrec 3ee9ce0529 test/test_targets: fix test_ulx3s name 2019-05-09 11:48:57 +02:00
Florent Kermarrec 74d37465b3 test/test_targets: comment bad variant tests for now 2019-04-29 17:11:42 +02:00
Florent Kermarrec 5c1d980540 soc/interconnect/axi: add burst support to AXI2Wishbone 2019-04-29 16:49:20 +02:00
Florent Kermarrec 6de2713524 soc/interconnect/axi: add capabilities to AXIBurst2Beat and simplify/optimize 2019-04-29 14:02:05 +02:00
Tim 'mithro' Ansell 5cbc5bc199 Adding testing of cpu variants. 2019-04-26 18:57:49 -05:00
Florent Kermarrec f7c0b118ce test/test_targets: cover all platforms 2019-04-23 11:38:18 +02:00
Florent Kermarrec 7d278854d5 global: switch to VexRiscv as the default CPU
VexRiscv can now replace LM32 for almost all usecases and we now have better
software support with RISC-V.
2019-04-22 09:41:07 +02:00
Florent Kermarrec 28d80bd641 ci: fix test_targets/test_simple 2019-04-22 08:53:43 +02:00
Florent Kermarrec b7f53fb93c test: remove waveforms generation 2019-04-22 08:41:28 +02:00
Florent Kermarrec e98ac680c1 travis: simplify, enable and add RISC-V toolchain to build targets 2019-04-22 08:32:00 +02:00
Florent Kermarrec 9cbed91b3e soc/interconnect/axi: add AXIBurst2Beat
Converts AXI bursts commands to AXI beats.
2019-04-19 12:13:16 +02:00
Florent Kermarrec ed2578799b test: add test_axi_lite (with test code from soc/interconnect/axi_lite lightly modified) 2019-02-27 22:24:56 +01:00
Florent Kermarrec 6a4c133cd2 test: add basic test_csr 2019-02-27 21:46:00 +01:00
Florent Kermarrec 68e1dfca28 boards: avoid duplicating platforms that can be found in migen/litex-buildenv
The platforms that are kept are the ones used for litex development.
2019-01-06 19:01:19 +01:00
Florent Kermarrec 5137c2bf88 test/test_targets: update 2018-11-17 17:36:57 +01:00
Florent Kermarrec a5ed42ec68 soc/interconnect/stream: add Gearbox 2018-11-17 17:29:45 +01:00
Florent Kermarrec 11d536dc4d test: remove test_bitslip (integrated in migen) 2018-11-17 17:29:09 +01:00
Florent Kermarrec 0b0e3ac1dd test/test_targets: test simple design with all platforms 2018-09-24 02:02:14 +02:00
Florent Kermarrec e04530e0c4 test/test_targets: update and reorganize targets 2018-09-24 01:15:33 +02:00
Florent Kermarrec 1925ba176f replace litex.gen imports with migen imports 2018-02-23 13:38:19 +01:00
Florent Kermarrec e0ce485a17 test/test_gearbox: continue, but we are hitting a simulator bug (related to clock domains declared in modules) 2017-04-25 10:57:34 +02:00
Florent Kermarrec 3ca0cb0cea test: add test_gearbox skeleton 2017-04-24 21:41:46 +02:00
Florent Kermarrec b4ebfb4031 test/test_targets: check top.v generation 2017-04-24 19:25:58 +02:00
Florent Kermarrec 35e3d93d9b test: add basic test_targets.py 2017-04-24 19:13:17 +02:00
Florent Kermarrec dc66dfcb55 test: add test_bitslip (initially in litedram) 2017-04-24 18:50:06 +02:00
Florent Kermarrec 96898f1b39 add test directory with test_code_8b10b.py (from misoc) 2017-04-24 18:46:55 +02:00