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7329 Commits

Author SHA1 Message Date
Leon Schuermann f2a622975a litex_sim/xgmii_ethernet: fix RX frame check sequence generation 
The rewritten XGMII Ethernet module generates proper frame check
sequences (FCS) on Ethernet frames received by the simulation, such
that the unmodified MAC pipeline including CRC checking can be
used. However, the byte order of the generated frame check sequence
has been inverted. This becomes apparent when one specifies that the
CRC should be calculated in the LiteX BIOS.

This fixes the byte order to be correct. The similar GMII Ethernet
module did not contain this mistake.

Fixes: 7b533a032d ("litex_sim: rewrite XGMII verilator...")
Signed-off-by: Leon Schuermann <leon@is.currently.online>
 2021-10-25 08:57:36 +02:00
Navaneeth Bhardwaj 2886fe1701
Add bios test mode for CI (#1076) 
* Add bios test mode for CI

This enables to test the booting of each CPU configurations with the bios in Verilator simulation.
 2021-10-24 12:08:58 +02:00
Florent Kermarrec 8e448592f0 interconnect/packet: Revert old last/ready logic handling (new one breaks test_packet) and comment out test_packet2 tests (does not seems to be working with previous last/ready handling). 2021-10-23 18:21:47 +02:00
Florent Kermarrec 59fd2d31c7 test/test_packet2: Fix imports. 2021-10-23 17:54:00 +02:00
Florent Kermarrec f3f9737697 interconnect/packet: Add FIXME notes. 2021-10-23 17:43:55 +02:00
Florent Kermarrec 32bb2554bc test: Rename new test_packet/stream to test_packet2/stream2 and revert old tests. 
Old and new tests are complementary and would need to be merged.
 2021-10-23 17:40:41 +02:00
enjoy-digital 434b3a3654
Merge pull request #1008 from lschuermann/dev/packetizer-last_be-fix 
{Dep,P}acketizer: properly handle last_be wraparound
 2021-10-23 17:33:29 +02:00
Florent Kermarrec af66f8d2ec litex_setup: Switch to pythondata-cpu-ibex. 2021-10-23 17:26:25 +02:00
enjoy-digital adc3aecc56
Merge pull request #1074 from navan93/use-ibex-main-repo 
Use ibex main repo
 2021-10-23 17:24:04 +02:00
Florent Kermarrec 68b67af1bd build/efinix/common: Add initial Tristate/SDRTristate support. 2021-10-22 20:02:17 +02:00
Florent Kermarrec 89b66be323 build/efinix/efinity: Fix Slice case on get_pin_location/get_pin_name. 2021-10-22 20:01:31 +02:00
Florent Kermarrec 62c7978cfd fhdl/verilog: Add optional platform parameter and set platform to specials. 
Being able to access the platform when lowering specials is required for Efinity.
 2021-10-22 20:00:27 +02:00
Florent Kermarrec 2a775e1493 efinix/efinity: Remove spi_low_power_mode (Prevents BIOS XiP). 2021-10-22 10:41:42 +02:00
Florent Kermarrec f7a256bc5b tools/litex_client: Add --length parameter for MMAP read accesses. 2021-10-22 09:07:19 +02:00
enjoy-digital 14c39c0f2b
Merge pull request #1075 from cr1901/sb_io-pin_input 
Set LatticeiCE40SDROutputImpl to `PIN_INPUT` mode.
 2021-10-22 09:05:26 +02:00
William D. Jones 140e4586ab Use PIN_INPUT mode in LatticeiCE40SDROutputImpl because i_INPUT_CLK is not connected. 2021-10-21 12:11:52 -04:00
Florent Kermarrec 6f8fbfb619 soc/add_cpu: Avoid checking variant with CPUNone. 2021-10-21 11:44:45 +02:00
Florent Kermarrec d16d4917d6 build/openfpgaloader: Allow reuse of programmer for consecutive commands and fix --offset. 
- Avoid appending to self.cmd on each load_bitstream/flash call to allow reused of programmer object.
- Convert address to str.
 2021-10-21 11:25:32 +02:00
Navaneeth Bhardwaj a7a746473d Fix missing include in ibex 
Change Ibex to use pythondata-cpu-ibex package and also fix the error of missing include by adding the dependency files first to the list of source files. As mentioned in  lowRISC/ibex#1461.
 2021-10-20 18:26:02 +05:30
Navaneeth Bhardwaj cf2e073b14 Add changes to use Ibex from pythondata-cpu-ibex 2021-10-20 07:28:13 +05:30
Florent Kermarrec 8fa4de5ede cores/video: Interpret CSI Move Up as Clear XY. 2021-10-19 17:24:41 +02:00
Florent Kermarrec 8945d74aa3 litex_setup: Bump pythondata-misc-opentitan (and update Get SHA1 command). 2021-10-19 15:47:24 +02:00
Florent Kermarrec b9545c2276 cpu/ibex: Add local patch to fix missing import. 2021-10-19 15:43:27 +02:00
enjoy-digital f4bd729d28
Merge pull request #1070 from navan93/ibex-irq-support 
Fix the support for Ibex.
 2021-10-19 15:43:12 +02:00
Florent Kermarrec 78237fffd9 cores/cpu: Avoid complex port types on microwatt_wrapper. 
microwatt_wrapper.vhdl was introduced for this since some toolchains don't
support complex VHDL ports types on verilog instances (ex previous version
of Vivado).
 2021-10-19 15:04:12 +02:00
Florent Kermarrec d1bb62b5fb litex_setup: Bump pythondata-cpu-microwatt to 0xdad611c. 2021-10-19 14:44:12 +02:00
enjoy-digital 2a97b6a1c1
Merge pull request #1067 from antmicro/fix-microwatt-synthesis 
Fix microwatt synthesis
 2021-10-19 14:43:11 +02:00
Florent Kermarrec 4335e305f7 cpu/mor1kx: Add or1k-linux to gcc_triple. 2021-10-19 14:42:15 +02:00
Florent Kermarrec 4494e98549 litex_setup: Add link to bootlin prebuilt PowerPC/OpenRisc toolchains. 2021-10-19 14:41:42 +02:00
enjoy-digital adf5665f21
Merge pull request #1072 from AndrewD/master 
efinix and general improvements
 2021-10-19 13:46:09 +02:00
Andrew Dennison a043b2536d efinix: abort if scripts fail 
* get obscure downstream errors when the scripts blindly continue
 2021-10-19 12:51:32 +11:00
Andrew Dennison f426872e0c efinix: read pll names from database 2021-10-19 12:51:32 +11:00
Andrew Dennison 1fd99b366a soc: report System clock to 3dp 2021-10-19 12:51:32 +11:00
Andrew Dennison 0e164bb23c build/generic_platform: include identifier in ValueError 
* show which identifier is incorrectly specified
 2021-10-19 12:49:05 +11:00
Navaneeth 0fbaa51c71 Change to common isr handler 2021-10-19 07:14:36 +05:30
Andrew Dennison 053e540b8a soc/csr: ValueError if write would be truncated in simulation 2021-10-19 10:42:52 +11:00
Andrew Dennison 04e9ffa2b2 soc/csr: Document simulation side effects of read/write 2021-10-19 10:42:52 +11:00
Florent Kermarrec 467c1b9b88 builder: Move Meson check to _check_meson and only do it when using BIOS. 2021-10-18 18:48:47 +02:00
Navaneeth ef8bab4c11 Add support for Ibex interrupt 
Initial support for a working Ibex interrupt. Tested in Verilator.
 2021-10-18 20:02:05 +05:30
Florent Kermarrec 2a109c3a3e integration/builder: Add Meson install/version check. 2021-10-18 08:41:51 +02:00
Florent Kermarrec f92a185109 litex_setup: Fix git checkout to specific version (we are using short sha1 hashes). 2021-10-18 08:19:11 +02:00
navaneeth c8a83461b4 Add initial changes to add IRQ support 
In the waveform IRQ pending seems to be going high but the call to ISR() doesn't happen.
 2021-10-17 12:32:31 +05:30
navaneeth b2b0ba66e5 Fix the support for Ibex. 
Take care of the module change in instantiation of Ibex core.
 2021-10-16 16:29:00 +05:30
enjoy-digital 57002cf3fc
Merge pull request #1069 from trabucayre/efinix_timing_model 
efinix: don't hardcode timing model
 2021-10-16 08:48:19 +02:00
Gwenhael Goavec-Merou 627363906c efinix: don't hardcode timing model 2021-10-16 07:20:17 +02:00
Florent Kermarrec 306bdcaed8 fhdl/verilog: Fix regression introduced in to_signed function. 2021-10-15 21:46:42 +02:00
enjoy-digital 942d3165bd
Merge pull request #1068 from mmicko/efinix_pgm_fix 
efinix: set defaults for efx_pgm pass
 2021-10-15 17:42:12 +02:00
Miodrag Milanovic 8692ddfbff Set defaults for efx_pgm pass 2021-10-15 16:40:01 +02:00
Florent Kermarrec 37dd6c1edb fhdl/verilog: Update header. 2021-10-15 15:25:23 +02:00
Florent Kermarrec 3b78fd928d fhdl/verilog: Remove blocking_assign (not used with LiteX). 2021-10-15 15:20:01 +02:00