60537fc39f
build/xilinx/yosys_nextpnr: fix f4pga_device for xc7a100 : xc7a35t -> xc7a100t
2023-05-18 12:13:29 +02:00
9c890a0a27
gen/fhdl/verilog: Simplify/Rename registers initialization parameter.
2023-05-17 17:24:06 +02:00
be1d64acaf
Merge pull request #1690 from bunnie/asic-target
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add an option to generate without reg initializers (asic targets)
2023-05-17 16:53:51 +02:00
fb0c9e846d
build/add_period_constraint: Simplify by using new integrated cases in generic add_period_constraint.
2023-05-17 16:45:45 +02:00
53a0bc92e4
build/generic_toolchain: Directly handle specific cases with clk None and differential clk.
2023-05-17 16:44:35 +02:00
a4eac2d360
Merge pull request #1691 from jersey99/clock-keep-optional
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Clock keep optional for XilinxPlatform
2023-05-17 16:36:47 +02:00
5115ec3513
Merge pull request #1692 from zyp/fix_dispatcher_single
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soc/interconnect/packet: Don’t bypass dispatcher with a single slave if it can be deselected.
2023-05-17 16:31:09 +02:00
91f56aaf0e
soc/interconnect/packet: Don’t bypass dispatcher with a single slave if it can be deselected.
2023-05-17 01:36:42 +02:00
6437c9e406
Merge remote-tracking branch 'upstream/master' into clock-keep-optional
2023-05-15 14:25:31 -07:00
4e15fd54b0
add an option to generate without reg initializers (asic targets)
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ASIC targets can't set a reg to a known value on boot, so for
more accurate simulations it would be nice to have an option
in the platform to specify generating the verilog without 'reg'
initializers. The presence of these initializers can mask
problems in simulations with X-prop that can lead to missing
explicit reset conditions.
2023-05-15 18:45:10 +08:00
782f045b16
Merge pull request #1689 from hansfbaier/master
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Avalon2Wishbone: Burst can only advance if write is high and waitrequest low
2023-05-11 08:27:40 +02:00
2b4c75ddd3
Avalon2Wishbone: Burst can only advance if write is high and waitrequest low
2023-05-11 08:24:12 +07:00
7d58f5d640
Merge pull request #1685 from hansfbaier/avalon-burst-test
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Assert readdatavalid on bursts in Avalon2WishboneMM test (fixes #1686 )
2023-05-10 11:12:36 +02:00
33fbf558a2
Merge branch 'master' into avalon-burst-test
2023-05-10 11:12:30 +02:00
82526460e9
Merge pull request #1684 from hansfbaier/retro-vga
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Add low res video modes
2023-05-10 11:09:46 +02:00
537b1b8530
Merge pull request #1683 from hansfbaier/master
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AvalonMM2Wishbone: use same addressing on avalon and wishbone, leave address translation to the user
2023-05-10 11:09:13 +02:00
ef904a14e1
AvalonMM2Wishbone: fix burst reads ( #1686 )
2023-05-10 05:22:49 +07:00
71a0e398a7
Avalon2Wishbone test: assert readdatavalid on bursts
2023-05-10 04:05:16 +07:00
90581a2f13
add some low resolution video modes
2023-05-09 15:29:27 +07:00
f00eb4e112
AvalonMM2Wishbone: use same addressing on avalon and wishbone, leave address translation to the user
2023-05-09 15:26:27 +07:00
3ab7ebe536
CHANGES.md: Release 2023.04.
2023-05-08 10:59:17 +02:00
3c03b6f5e4
avalon/AvalonMM2Wishbone: Fix avl.readdatavalid.
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Multi-driven, remove assign in BURST-READ.
2023-05-08 10:18:56 +02:00
dd40c25b23
avalon/AvalonMM2Wishbone: Fix write byteenable/sel.
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From mnl_avalon_spec.pdf:
"The byteenables can change for different words of the burst."
2023-05-08 10:03:51 +02:00
f7ee9fad96
avalon/AvalonMM2Wishbone: Do other cosmetic changes.
2023-05-08 09:57:35 +02:00
9f44a498d6
avalon/AvalonMM2Wishbone: Simplify wb.cti.
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In BURST-WRITE/READ, wb.cti can't be BURST_NONE.
2023-05-08 09:42:12 +02:00
a62149831d
avalon/AvalonMM2Wishbone: Avoid reseting burst_set (not useful since always set before use).
2023-05-08 09:29:02 +02:00
451fb8d378
avalon/AvalonMM2Wishbone: Directly set burst_read in BURST-READ state.
2023-05-08 09:27:05 +02:00
8e1a3880d3
interconnect/avalon: Switch to directory/python package and split mm/st.
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Similarly to what is done for AXI and will avoid too complex/large files.
2023-05-08 09:25:16 +02:00
7071304b10
soc/interconnect/avalon/AvalonMM: Do a first cosmetic cleanup pass.
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- Add separators.
- Use coding style similar to other modules.
- Replace the Mux with simpler If/Else constructs to improve understanding and readability.
2023-05-08 09:14:35 +02:00
c5c7e86cca
WIP AvalonMM interface and Avalon to Wishbone Bridge ( #1674 )
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Add initial AvalonMM interface and AvalonMM2Wishbone.
2023-05-08 08:42:10 +02:00
85ee31aae7
setup.py: Prepare for 2023.04.
2023-05-07 20:54:04 +02:00
0f1ad8dcfc
CHANGES.md: Update.
2023-05-05 10:08:11 +02:00
f62d380b2f
build/yosys_wrapper: Skip language=None files.
2023-05-03 17:33:16 +02:00
8f26e5f7a8
tools/litex_client: Add binded property to simplify user scripts.
2023-05-03 17:33:12 +02:00
34ec22f8ab
Merge pull request #1677 from mntmn/master
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bios/spiflash: fix write/ erase, add write from sdcard and range erase
2023-04-26 07:11:54 +02:00
1b7d229668
Merge branch 'master' of https://github.com/enjoy-digital/litex
2023-04-25 17:15:44 +02:00
e23fe832f0
litespi/flash: fix status reg read; remove delays
2023-04-25 17:05:33 +02:00
cb2a789008
bios/spiflash: bring back write and erase, add write from sdcard file cmd
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When shipping MNT RKX7, I pre-flash the SPI flash with a LiteX bitfile
for testing. cmd_spiflash had regressed because of changed SPIFLASH defines
and didn't offer the write functions anymore. This commit fixes that, and
adds convenience functions:
- flash_erase_range <offset> <count (bytes)>
- flash_from_sdcard <filename>
The latter reuses some boot code to copy the contents of the specified
file from the boot FAT partition on the SD card to SPI flash (i.e.
a bitstream).
2023-04-25 13:30:07 +02:00
118dd6ed08
liblitespi/spiflash: add erase and write functions
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The code is based on norbert thiel's comment https://github.com/litex-hub/litespi/issues/52
But edited to work with W25Q128JVS flash used in MNT RKX7.
2023-04-25 13:26:18 +02:00
309f012d2c
cores/usb_ohci: Ensure self.usb_clk_freq is an integer (as a workaround to prevent build issue).
2023-04-24 10:31:47 +02:00
0976c5aa54
Refactor code
2023-04-20 19:00:26 +08:00
4731aa6522
Add missing ifdef check
2023-04-20 18:46:50 +08:00
89396c7586
Add SDRAM_PHY_CLAM_SHELL guard
2023-04-20 18:45:12 +08:00
11dc5b049b
Working clam shell topology
2023-04-20 18:35:56 +08:00
b367c27191
integration/soc/zynq: Revert previous commit (incorrect), re-enable CSR decode on Zynq7000/MP and add check/error when SoCBusHandler has more than one Region and one of them has its decoder disabled.
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This will prevent silent errors and means offset needs to be added in Software.
2023-04-12 19:54:01 +02:00
f44ff2bac4
integration/soc/SoCBusHandler: Force interconnect to Crossbar when at least one region has the decoder disabled.
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See https://github.com/enjoy-digital/litex/issues/1665 since optimizations on Shared Interconnect can't be used with
disabled decoder.
2023-04-12 19:13:14 +02:00
cb9f01be9e
Merge pull request #1671 from hansfbaier/master
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give human readable error messages if a connector or pin is not available
2023-04-11 16:34:46 +02:00
748899aa49
Merge pull request #1670 from dasdgw/i2c_fix
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soc/software: fix i2c_write
2023-04-11 16:34:18 +02:00
750f8c41b9
distinguish between dict and list connectors in error message
2023-04-11 14:11:48 +07:00
cfaba189c4
give human readable error messages if a connector or pin is not available
2023-04-11 11:09:10 +07:00
Gwenhael Goavec-Merou
Florent Kermarrec
Vegard Storheil Eriksen
Vamsi Vytla
bunnie
Hans Baier
Lukas F. Hartmann
Jiajie Chen