Sebastien Bourdeauducq
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f53acb92e7
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fhdl/autofragment: fix submodules
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2013-03-09 21:15:38 +01:00 |
Sebastien Bourdeauducq
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6da8eb906f
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fhdl/autofragment: empty build_fragment by default
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2013-03-09 19:10:47 +01:00 |
Sebastien Bourdeauducq
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2b8dc52c13
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Use common definition for FinalizeError
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2013-03-09 19:03:13 +01:00 |
Sebastien Bourdeauducq
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b75fb7f97c
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csr/SRAM: support for writes with memory widths larger than bus words
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2013-03-09 00:50:57 +01:00 |
Sebastien Bourdeauducq
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6fa30053bf
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fhdl/verilog: tristate outputs are always wire
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2013-03-06 11:30:52 +01:00 |
Sebastien Bourdeauducq
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9b4ca987e0
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bus/csr: support memories with larger word width than the bus (read only)
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2013-03-03 19:27:13 +01:00 |
Sebastien Bourdeauducq
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bb5ee8d3bd
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fhdl/autofragment: bugfixes + add auto_attr
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2013-03-03 17:53:06 +01:00 |
Sebastien Bourdeauducq
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cc8118d35c
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fhdl/autofragment: FModule
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2013-03-02 23:30:54 +01:00 |
Sebastien Bourdeauducq
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d2491828a4
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csr/SRAM: prefix page register with memory name
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2013-03-01 12:06:12 +01:00 |
Sebastien Bourdeauducq
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c10622f5e2
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fhdl/verilog: insert reset before listing signals
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2013-02-27 18:10:04 +01:00 |
Sebastien Bourdeauducq
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d2cbc70190
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bank/description: memprefix
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2013-02-25 23:14:15 +01:00 |
Sebastien Bourdeauducq
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a81781f589
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fhdl/specials: allow setting memory name
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2013-02-25 23:14:03 +01:00 |
Sebastien Bourdeauducq
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425de02f42
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uio/ioo: fix specials
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2013-02-25 23:13:38 +01:00 |
Sebastien Bourdeauducq
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55ab01f928
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fhdl/specials/Instance: _printintbool -> verilog_printexpr
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2013-02-24 13:08:01 +01:00 |
Sebastien Bourdeauducq
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a878db1e3c
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genlib: clock domain crossing elements
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2013-02-23 19:03:35 +01:00 |
Sebastien Bourdeauducq
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7c4e6c35e5
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fhdl/verilog: support special lowering and overrides
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2013-02-23 19:03:16 +01:00 |
Sebastien Bourdeauducq
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f9acee4e68
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corelogic -> genlib
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2013-02-22 23:19:37 +01:00 |
Sebastien Bourdeauducq
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38664d6e16
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fhdl: inline synthesis directive support
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2013-02-22 19:10:02 +01:00 |
Sebastien Bourdeauducq
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49cfba50fa
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New 'specials' API
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2013-02-22 17:56:35 +01:00 |
Sebastien Bourdeauducq
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1b18194b1d
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fhdl: TSTriple
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2013-02-19 17:26:02 +01:00 |
Sebastien Bourdeauducq
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dc93a231c6
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fhdl: tristate support
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2013-02-15 00:17:24 +01:00 |
Sebastien Bourdeauducq
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63d399b6ad
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fhdl/autofragment: from_attributes
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2013-02-11 18:34:01 +01:00 |
Sebastien Bourdeauducq
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92b67df41c
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sim: default runner to Icarus Verilog
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2013-02-09 17:04:53 +01:00 |
Sebastien Bourdeauducq
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bd6856ba7a
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flow/perftools: finish removing ActorNode
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2013-02-09 17:03:48 +01:00 |
Sebastien Bourdeauducq
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473fd20f8c
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fhdl/structure: store clock domain name
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2013-01-24 13:49:49 +01:00 |
Sebastien Bourdeauducq
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3201554f76
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fhdl/verilog: fix spurious clock/reset signals on multiple calls to convert()
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2013-01-23 15:13:06 +01:00 |
Sebastien Bourdeauducq
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314a6c7743
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corelogic: complex arithmetic support
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2013-01-05 14:18:36 +01:00 |
Sebastien Bourdeauducq
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badba89686
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fhdl: support nested statement lists
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2013-01-05 14:18:15 +01:00 |
Sebastien Bourdeauducq
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47f5fc70e4
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pytholite: fix bug with constant assignment to register
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2012-12-19 16:21:57 +01:00 |
Sebastien Bourdeauducq
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9c65402fda
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pytholite: prune unused registers
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2012-12-19 16:03:05 +01:00 |
Sebastien Bourdeauducq
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3fae6c8f03
|
Do not use super()
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2012-12-18 14:54:33 +01:00 |
Sebastien Bourdeauducq
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b06fbdedd6
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fhdl/tools: bitreverse
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2012-12-14 23:56:16 +01:00 |
Sebastien Bourdeauducq
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1f350adf14
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actorlib/sim/SimActor: do not drive busy low when generator yields None
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2012-12-14 23:56:03 +01:00 |
Sebastien Bourdeauducq
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a67f483f0f
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Token: support idle_wait
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2012-12-14 19:16:22 +01:00 |
Sebastien Bourdeauducq
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6f99241585
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Move Token to migen.flow.transactions
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2012-12-14 15:55:38 +01:00 |
Sebastien Bourdeauducq
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28b4d99d31
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replace some forgotten is_abstract()
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2012-12-12 22:36:45 +01:00 |
Sebastien Bourdeauducq
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a7227d7d2b
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Remove ActorNode
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2012-12-12 22:20:48 +01:00 |
Sebastien Bourdeauducq
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8163ed4828
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Merge branch 'master' of github.com:milkymist/migen
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2012-12-06 20:57:30 +01:00 |
Sebastien Bourdeauducq
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483b821342
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fhdl/structure: do not create Signal in Instance when parameter is int
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2012-12-06 20:56:46 +01:00 |
Sebastien Bourdeauducq
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280a87ea69
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elsewhere: do not create interface in default param
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2012-12-06 17:34:48 +01:00 |
Sebastien Bourdeauducq
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62187aa23d
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migen/bank: do not create interface in default param
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2012-12-06 17:28:28 +01:00 |
Sebastien Bourdeauducq
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c3fdf42825
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bus/csr: add SRAM
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2012-12-06 17:16:17 +01:00 |
Sebastien Bourdeauducq
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e89c66bf14
|
bank/csrgen: interface -> bus
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2012-12-06 17:15:34 +01:00 |
Sebastien Bourdeauducq
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273d9d285b
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bank/description: define reset value of read signal
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2012-12-05 16:40:44 +01:00 |
Sebastien Bourdeauducq
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34ce934809
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actorlib/sim: drive busy high until generator is finished
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2012-12-05 16:40:12 +01:00 |
Sebastien Bourdeauducq
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4bcb39699b
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bus/wishbone/sram: accept memories < 32 bits
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2012-12-01 13:04:22 +01:00 |
Sebastien Bourdeauducq
|
523816982a
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bus/wishbone: add SRAM
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2012-12-01 12:59:09 +01:00 |
Sebastien Bourdeauducq
|
adb1565d7a
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pytholite: fix bit width of selection signal
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2012-11-30 17:07:32 +01:00 |
Sebastien Bourdeauducq
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cfb23c442f
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pytholite: support signed registers
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2012-11-30 17:07:12 +01:00 |
Sebastien Bourdeauducq
|
7093939309
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corelogic/roundrobin: fix request width (again)
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2012-11-29 23:47:51 +01:00 |