Florent Kermarrec
7a4fa58cbf
CHANGES: Update.
2023-06-13 18:37:34 +02:00
Florent Kermarrec
57840c63a3
cores/clock/xilinx_common: Add BUFH support and lower buf parameter before use to allow user to specify it in upper or lower case.
2023-06-13 13:23:47 +02:00
Florent Kermarrec
3a7aaf5124
cores/code_8b10b: Add D function.
2023-06-13 10:00:37 +02:00
Florent Kermarrec
a7ba5771b1
integration/soc/add_etherbone: Fix typo.
2023-06-09 15:18:23 +02:00
Florent Kermarrec
c6adf703a3
CHANGES.md: Update.
2023-06-06 11:09:44 +02:00
Andrew Dennison
e84881072f
software/liblitespi: fix building with debug
2023-06-06 10:02:50 +02:00
Andrew Dennison
9c426c14a2
software/liblitespi: add read_id()
2023-06-06 10:02:37 +02:00
Andrew Dennison
d0b7f54d27
build/openfpgaloader: support --fpga-part
2023-06-06 10:02:25 +02:00
Andrew Dennison
bd7b951af0
soc/software/liblitesdcard: be less verbose
...
debug is now more usable:
Booting from SDCard in SD-Mode...
Booting from boot.json...
Setting SDCard clk freq to 781 KHz
CMD0: GO_IDLE
cmdevt: wait for event & 0x1
cmdevt: 00000001
00000000 00000000 00000000 00000000
CMD8: SEND_EXT_CSD, arg: 0x000001aa
cmdevt: wait for event & 0x1
cmdevt: 00000005
00000000 00000000 00000000 00000000
Booting from boot.bin...
Setting SDCard clk freq to 781 KHz
CMD0: GO_IDLE
cmdevt: wait for event & 0x1
cmdevt: 00000001
00000000 00000000 00000000 00000000
CMD8: SEND_EXT_CSD, arg: 0x000001aa
cmdevt: wait for event & 0x1
cmdevt: 00000005
00000000 00000000 00000000 00000000
SDCard boot failed.
No boot medium found
2023-06-06 10:02:03 +02:00
Andrew Dennison
51dd5277af
soc/integration: support software_debug for add_spi_flash()
2023-06-06 10:01:38 +02:00
Andrew Dennison
93bc2760fe
build/openfpgaloader: support jtag index-chain
...
* allows loading a FPGA that is not the only device in a JTAG scan chain
2023-06-06 10:01:21 +02:00
Andrew Dennison
d60f5c221c
build/efinity: document SLEW 1 is fast
2023-06-06 10:00:49 +02:00
Andrew Dennison
f8a604e0fa
build/efinity: assert DRIVE_STRENGTH is valid
...
With invalid drive strength Efinity 2021.2 fails with an unhelpful message:
"WARNING: Fail to generate summary report file"
Efinity 2022.2 does report DRIVE_STRENGTH is invalid
2023-06-06 10:00:27 +02:00
Andrew Dennison
8066a9e265
efinix/dbparser: support more Titanium pll_in pins
...
* Veridied to fix using A11 on Ti60F255. Without this the wrong GPIO was silently used
* Seems to correctly select PLL_IN clock for these Ti60F255 pins:
** H6, B2, C5, E6, A11, C14, L11, R13, P11, R5, A2
2023-06-06 08:51:41 +02:00
Andrew Dennison
e10643bfd5
yosys: add command line arg to be quiet
2023-06-06 08:51:22 +02:00
Andrew Dennison
4eed62143c
litex_client: remove duplicate read
2023-06-06 08:49:54 +02:00
Andrew Dennison
5e667f17d7
csr: fix field access check
...
* Broken in 5dc440e80d
2023-06-06 08:49:32 +02:00
Richard Tucker
88ec1b3f5e
tools: include LITESD in zephyr dts generator
2023-06-06 08:42:49 +02:00
Andrew Dennison
eb67197a46
tools/linux: fix dts warning: missing #address-cells
2023-06-06 08:42:35 +02:00
Andrew Dennison
9b67898e99
tools/linux: add sys_clk to device tree
...
* required for using standard devm_clk_get() clock mechanism in linux drivers
2023-06-06 08:41:58 +02:00
Andrew Dennison
200a1a18ee
soc/software: move helpers to hw/common.h
...
Fixes warning:
liblitespi/spiflash.c: In function 'spiflash_erase_range':
liblitespi/spiflash.c:202:4: warning: implicit declaration of function 'cdelay' [-Wimplicit-function-declaration]
cdelay(CONFIG_CLOCK_FREQUENCY/25);
^~~~~~
Fixes link failure with spiflash and without liblitedram after commit: 118dd6ed08
2023-06-06 08:41:35 +02:00
Florent Kermarrec
d8ba2e8f65
build/xilinx/vivado: Add project commands to add commands just after project creation.
2023-06-05 14:20:59 +02:00
Florent Kermarrec
a1106b997e
soc/add_spi_sdcard: Fix broken/useless add_module.
...
Was already useless before and raise a valid assertion.
2023-06-04 08:19:15 +02:00
enjoy-digital
e5f790f29f
Merge pull request #1699 from bjonnh/fix_lattice_programmer
...
Fix frequency specification for ECPDAP on Lattice
2023-05-30 10:41:23 +02:00
Florent Kermarrec
93b45a687f
interconnect/stream/Pipeline: Finalize Pipeline if modules are provided during __init__ (for retro-compatibility).
2023-05-30 08:25:08 +02:00
Jonathan Bisson
eb8e43359d
Fix frequency specification for ECPDAP on Lattice
...
It was given as kHz but it takes Hz
2023-05-27 18:59:07 -05:00
Florent Kermarrec
2a27ca18ea
stream/Pipeline: Allow Pipeline to be created dynamically.
...
Ex:
self.submodules.pipeline = Pipeline()
self.pipeline.add(m0)
self.pipeline.add(m1)
self.pipeline.add(m3)
2023-05-26 10:17:02 +02:00
enjoy-digital
c6ccb626e8
Merge pull request #1673 from jiegec/vcu128
...
Add support for clam shell topology
2023-05-25 22:22:56 +02:00
enjoy-digital
57bffbbb92
Merge pull request #1697 from hansfbaier/master
...
AvalonMM/AvalonMM2Wishbone: fix read bursts (readdatavalid one cycle too short)
2023-05-22 19:22:56 +02:00
Hans Baier
6ad14ef644
AvalonMM/AvalonMM2Wishbone: fix read bursts (readdatavalid one cycle too short)
2023-05-22 10:04:38 +07:00
Florent Kermarrec
54192651d8
build/xilinx/ise/add_period_constraint: Add keep parameter.
2023-05-21 09:33:19 +02:00
Florent Kermarrec
f5a9efd8ba
build/add_period_constraint: Fix trellis (thanks bjonnh and zyp) and avoid specific add_period_constraint in libero_soc.
2023-05-21 09:06:20 +02:00
Gwenhael Goavec-Merou
60537fc39f
build/xilinx/yosys_nextpnr: fix f4pga_device for xc7a100 : xc7a35t -> xc7a100t
2023-05-18 12:13:29 +02:00
Florent Kermarrec
9c890a0a27
gen/fhdl/verilog: Simplify/Rename registers initialization parameter.
2023-05-17 17:24:06 +02:00
enjoy-digital
be1d64acaf
Merge pull request #1690 from bunnie/asic-target
...
add an option to generate without reg initializers (asic targets)
2023-05-17 16:53:51 +02:00
Florent Kermarrec
fb0c9e846d
build/add_period_constraint: Simplify by using new integrated cases in generic add_period_constraint.
2023-05-17 16:45:45 +02:00
Florent Kermarrec
53a0bc92e4
build/generic_toolchain: Directly handle specific cases with clk None and differential clk.
2023-05-17 16:44:35 +02:00
enjoy-digital
a4eac2d360
Merge pull request #1691 from jersey99/clock-keep-optional
...
Clock keep optional for XilinxPlatform
2023-05-17 16:36:47 +02:00
enjoy-digital
5115ec3513
Merge pull request #1692 from zyp/fix_dispatcher_single
...
soc/interconnect/packet: Don’t bypass dispatcher with a single slave if it can be deselected.
2023-05-17 16:31:09 +02:00
Vegard Storheil Eriksen
91f56aaf0e
soc/interconnect/packet: Don’t bypass dispatcher with a single slave if it can be deselected.
2023-05-17 01:36:42 +02:00
Vamsi Vytla
6437c9e406
Merge remote-tracking branch 'upstream/master' into clock-keep-optional
2023-05-15 14:25:31 -07:00
bunnie
4e15fd54b0
add an option to generate without reg initializers (asic targets)
...
ASIC targets can't set a reg to a known value on boot, so for
more accurate simulations it would be nice to have an option
in the platform to specify generating the verilog without 'reg'
initializers. The presence of these initializers can mask
problems in simulations with X-prop that can lead to missing
explicit reset conditions.
2023-05-15 18:45:10 +08:00
enjoy-digital
782f045b16
Merge pull request #1689 from hansfbaier/master
...
Avalon2Wishbone: Burst can only advance if write is high and waitrequest low
2023-05-11 08:27:40 +02:00
Hans Baier
2b4c75ddd3
Avalon2Wishbone: Burst can only advance if write is high and waitrequest low
2023-05-11 08:24:12 +07:00
enjoy-digital
7d58f5d640
Merge pull request #1685 from hansfbaier/avalon-burst-test
...
Assert readdatavalid on bursts in Avalon2WishboneMM test (fixes #1686 )
2023-05-10 11:12:36 +02:00
enjoy-digital
33fbf558a2
Merge branch 'master' into avalon-burst-test
2023-05-10 11:12:30 +02:00
enjoy-digital
82526460e9
Merge pull request #1684 from hansfbaier/retro-vga
...
Add low res video modes
2023-05-10 11:09:46 +02:00
enjoy-digital
537b1b8530
Merge pull request #1683 from hansfbaier/master
...
AvalonMM2Wishbone: use same addressing on avalon and wishbone, leave address translation to the user
2023-05-10 11:09:13 +02:00
Hans Baier
ef904a14e1
AvalonMM2Wishbone: fix burst reads ( #1686 )
2023-05-10 05:22:49 +07:00
Hans Baier
71a0e398a7
Avalon2Wishbone test: assert readdatavalid on bursts
2023-05-10 04:05:16 +07:00
