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Dolu1990-patch-1

Dolu1990-patch-2

Dolu1990-patch-3

allows_clk_name_override

ci-cpus

ci-cva6

ci-dev-test

ci-openrisc

ctu-can-fd

dma_nax

efinix_fixes

efinix_fixes2

efinix_iface_signal_names

export_csr_c_rework

framebuffer_change

generic_toolchain

ghdl_fix

gowin_emcu_uart

hyperbus_2x

hyperbus_io_regs

hyperbus_variable_latency

hyperram_decoupling

hyperram_new

kianv

liteeth_wishbone_tx_rx_buses

master

multi-channel-pwm

naxriscv-merge

naxriscv_update

neorv32_litex_wrapper

neorv32_params

urv

usb_ohci_phy_fix

verilog_improvements

verilog_improvements_2

vexriscv_smp_irqs

video_framebuffer_skip_first_frame

video_mod_fix

wishbone_dma_ctrl

wishbone_word_byte_addressing

wuff

zynqmp_aximaster_eth_i2c_uart

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Mono Color

• c55521610c
  Merge 0986cd818c into 10dcc73676 fjullien 2024-11-22 05:38:10 +0000
• 8ef595be93
  Merge 35a8c8f9f6 into 10dcc73676 DaveBerkeley 2024-11-22 05:37:50 +0000
• 025396f3bb
  Merge 8fb6fc9008 into 10dcc73676 Leon Schuermann 2024-11-22 05:36:58 +0000
• 6e21705a37
  Merge b0e05b4533 into 10dcc73676 Geert Uytterhoeven 2024-11-22 05:35:18 +0000
• 1ac1c83b51 Fix vdb path for Efinity 2024.2 Matthias Breithaupt 2024-11-21 14:27:58 +0100
• b97d5b2fe0
  Merge 019b143854 into 10dcc73676 AndrewD 2024-11-20 22:05:15 +0800
• 915a10c5e1
  Merge a8920c7df8 into 10dcc73676 mkuhn99 2024-11-19 17:31:08 -0800
• 10dcc73676
  Merge pull request #2125 from trabucayre/ecp5_diamond_tristate enjoy-digital 2024-11-18 12:40:24 +0100
• 52148c7aad soc/integration/soc_core: Fix with_uartbone changes. Florent Kermarrec 2024-11-18 11:07:51 +0100
• 211ce59df4 build/lattice/common.py: added Tristate support for ECP5 when build with diamond Gwenhael Goavec-Merou 2024-11-17 11:32:33 +0100
• 8041969e00
  Merge pull request #2100 from VOGL-electronic/efinix_io_optimize enjoy-digital 2024-11-15 09:38:50 +0100
• 8399c919bd
  Merge pull request #2122 from acceleratedtech/accelerated/uart-dynamic-baudrate-for-upstream enjoy-digital 2024-11-15 09:36:20 +0100
• e9b02f2bf9
  Merge 8d68c1ada3 into 2b3fd723a2 Dmitry 2024-11-13 20:26:13 +0000
• 2b3fd723a2
  Merge pull request #2101 from VOGL-electronic/bios_spi_fix enjoy-digital 2024-11-13 11:12:51 +0100
• 0f45ea221e
  Merge pull request #2119 from long-pham/pr_useAllCPUCores enjoy-digital 2024-11-12 21:45:07 +0100
• e9e0140c74
  Merge pull request #2118 from long-pham/pr_openfpgaloader enjoy-digital 2024-11-12 21:40:57 +0100
• 8ece14849a
  Merge pull request #2117 from long-pham/main enjoy-digital 2024-11-12 21:40:25 +0100
• d7a8743f20
  Merge pull request #2123 from trabucayre/vhd2vconverter_libraries enjoy-digital 2024-11-12 21:38:38 +0100
• f056f37c29
  Merge pull request #2120 from juiceRv/fix/veril-fst-trace enjoy-digital 2024-11-12 21:37:09 +0100
• f731b36c9b build/vhd2v_converter.py: allows users to pass a list of libraries files to compile before convert HDL. Gwenhael Goavec-Merou 2024-11-09 07:55:18 +0100
• 9f7186a002
  Merge branch 'enjoy-digital:master' into master John_Tito 2024-11-09 09:57:56 +0800
• f53178d712 feat: add uart_with_dynamic_baudrate to SoCCore Jamey Hicks 2024-10-28 15:04:28 -0400
• c22e8d8a0b
  Merge a47bbb28f5 into 8b4949edcd Joshua Wise 2024-11-08 21:31:37 +0100
• 5fa144ec3a Fixes: Fix no close trace file when the sim is finished Li.XiongHui 2024-11-07 14:21:14 +0800
• 9cc8bf9866
  Switch to using MMCME4_ADV in USPMMCM to enable finer-grained clock output control Long Pham 2024-11-06 13:48:56 -0800
• 8b4949edcd
  Merge pull request #2115 from CKeilbar/soc-region-check-fix enjoy-digital 2024-11-06 22:29:05 +0100
• de9d3ab314 soc/cores/cpu/urv: Add DataBusToWishbone and use it. Florent Kermarrec 2024-11-06 21:59:11 +0100
• 2b3913982c soc/cores/cpu/urv: Add InstructionBusToWishbone and use it. Florent Kermarrec 2024-11-06 21:49:39 +0100
• d8e168a81f
  Enhance software build performance by utilizing all available CPU cores in the builder Long Pham 2024-11-06 11:35:28 -0800
• 935326e66c
  Add FTDI serial number option to openfpgaloader, useful when multiple similar boards are connected for CI/CD Long Pham 2024-11-06 11:25:54 -0800
• 82c10f58e8
  Merge branch 'enjoy-digital:master' into todo_pr long-pham 2024-11-06 11:16:53 -0800
• f47d09496a Add "--depth" and "-b" arguments for git clone command johntito 2024-11-06 10:34:43 +0800
• 1204cfda9d soc/cores/cpu/urv: Fix add_sources. Florent Kermarrec 2024-11-05 17:33:32 +0100
• 20b0e98fe0 cpu/urv: Fix Instruction Bus conversion to Wishbone and only keep it now that working. Florent Kermarrec 2024-11-05 16:46:23 +0100
• f15e2d5cba
  Merge bb2284b40b into 0170462fe8 Dmitry 2024-11-04 18:07:49 -0500
• e9613499ea Fix SOC region range check Chris Keilbart 2024-11-04 12:01:29 -0800
• 0170462fe8 soc/cores/jtag: Fix/Test p_init/p_INIT workaround. Florent Kermarrec 2024-11-04 14:34:28 +0100
• 3f3249cdf0
  Merge pull request #2113 from trabucayre/toolchain_diamond_sdc enjoy-digital 2024-11-04 12:53:48 +0100
• 47e8b0273f litex/build/lattice/diamond, platform: allows users to add custom sdc files Gwenhael Goavec-Merou 2024-11-04 12:42:38 +0100
• 175e63ac4c soc/cores/jtag: Add p_INIT/p_init workaround on ECP5JTAG to support Diamond and Trellis toolchains without manual changes. Florent Kermarrec 2024-11-04 12:40:39 +0100
• e2d1ebb686
  builder uses all cpu, use MMCME4_ADV for USPMMCM, add ftdi_serial option to openfpgaloader Long Pham 2024-10-30 22:25:40 -0700
• 4368d5a9ed test/test_led: Comment out TestWS1812 test since seems broken, will need to be investigated/fixed. Florent Kermarrec 2024-10-28 21:51:42 +0100
• 61ab30a739 soc/cores/jtag: Revert p_INIT since not tested. Florent Kermarrec 2024-10-28 20:05:47 +0100
• 10184ad325
  Merge pull request #2097 from trabucayre/build_diamond_addition enjoy-digital 2024-10-28 20:05:01 +0100
• 23df960859
  Merge pull request #2102 from Dolu1990/vexiiriscv-macsg enjoy-digital 2024-10-28 20:03:06 +0100
• dd092863f8
  Merge branch 'master' into vexiiriscv-macsg enjoy-digital 2024-10-28 20:02:56 +0100
• 18714dfca3
  Merge pull request #2104 from andelf/fix/ws2812-of-1-led enjoy-digital 2024-10-28 19:53:25 +0100
• e2bf669d6c bios: add flash_transfer_cmd Christian Klarhorst 2024-10-26 17:10:34 +0200
• 59fc1caac4
  Merge pull request #2099 from VOGL-electronic/vexiiriscv_sbi Dolu1990 2024-10-25 14:26:02 +0200
• 773fb34079
  vexiiriscv: have opensbi behind a option Fin Maaß 2024-10-18 07:58:44 +0200
• 8c7e510473 Fixes #2103: calculate memory depth for WS2812 Andelf 2024-10-25 11:43:49 +0800
• 24db36ced5 Merge remote-tracking branch 'origin/master' into wuff Dolu1990 2024-10-24 16:02:52 +0200
• 375940ad7d soc/core/vexiiriscv: add macsg support (dma based ethernet) wuff Dolu1990 2024-10-24 16:00:51 +0200
• d7bf75a75c
  bios: litespi: add newline to debug output Fin Maaß 2024-10-24 15:12:12 +0200
• 63fa4fda85
  bios: litespi: clear rx queue after write Fin Maaß 2024-10-24 15:10:37 +0200
• 54973eb9cb
  build: efinix: use constant output option Fin Maaß 2024-10-23 11:55:22 +0200
• 2d96e99494
  build: io: SDRTristate: move check Fin Maaß 2024-10-23 11:18:57 +0200
• 70f4a349e5
  efinix: ifacewriter: fix in output Fin Maaß 2024-10-23 11:10:16 +0200
• d6eec8e76d
  efinix: ifacewriter: gpio: share common code Fin Maaß 2024-10-23 11:08:58 +0200
• c1225736a8
  Merge pull request #2098 from enjoy-digital/urv enjoy-digital 2024-10-17 19:45:44 +0200
• 5f463dba87 CHANGES.md: Update. urv Florent Kermarrec 2024-10-17 17:45:50 +0200
• aab8912f5a soc/cores/cpu/urv: Move ROM init to builder and allow switching between classical ROM or ROM integrated in CPU. Florent Kermarrec 2024-10-17 17:44:40 +0200
• 9449d25911 soc/cores/cpu/urv: Able to boot LiteX BIOS with im bus connected to synchronous memory. - Replace im bus wishbone adaptation with synchronous memory (for now and initial tests). - Correctly handle dm bus wishbone adaptation (Added FIFO). Florent Kermarrec 2024-10-17 16:54:20 +0200
• edb56e73aa soc/cores/cpu: Add initial uRV CPU support (not yet working). Florent Kermarrec 2024-10-16 22:24:07 +0200
• 06f9f9780d litex/soc/cores/jtag.py: lattice target: INIT -> init (otherwise fails with diamond) Gwenhael Goavec-Merou 2024-10-16 13:47:42 +0200
• ea81314866 build/lattice/diamond.py,platform.py: allows adding custom strategy Gwenhael Goavec-Merou 2024-10-16 13:46:43 +0200
• 331e1938c9 build/lattice/diamond.py,platform.py: allows adding lattice's IPs Gwenhael Goavec-Merou 2024-10-16 13:45:57 +0200
• c4943c1c5d build/lattice/diamond.py: allows adding addition ldf commands in tcl Gwenhael Goavec-Merou 2024-10-16 13:44:20 +0200
• c82fddf635 CHANGES.md: Update. Florent Kermarrec 2024-10-15 12:54:37 +0200
• d5e4f9e975 soc/core/vexiiriscv : bring back xilinx support Dolu1990 2024-10-15 09:36:24 +0200
• 7f04cafe08 soc/cores/cpu/zynqmp/core.py: add_ethernet: added gt_location required by SGMII Gwenhael Goavec-Merou 2024-10-10 17:28:29 +0200
• 2935b7afb1 soc/cores/cpu/zynqmp/core.py: added missing pps signals Gwenhael Goavec-Merou 2024-10-10 17:26:35 +0200
• dc3364a3c7 CHANGES.md: Update. Florent Kermarrec 2024-10-09 16:42:05 +0200
• 01c7a78f67
  Merge pull request #2095 from trabucayre/zynqmp_ethernet_sgmii enjoy-digital 2024-10-09 16:38:33 +0200
• ddb8d16381 soc/cores/cpu/zynqmp/core.py: added support for SGMII via PL with option PTP support Gwenhael Goavec-Merou 2024-10-09 16:14:31 +0200
• 34b98ab578
  Merge pull request #2093 from mgaggero/feature-alpine-linux Gwenhael Goavec-Merou 2024-10-09 06:32:05 +0200
• e148650279 Fixes #2092: provides support for riscv gcc installation on Alpine Linux. Massimo Gaggero 2024-10-08 20:46:38 +0200
• bc3e90c93a
  Merge pull request #2090 from VOGL-electronic/efinix_iobank Gwenhael Goavec-Merou 2024-10-08 09:54:20 +0200
• d26994916d
  build: efinix: use ifacewriter to set bank voltage Fin Maaß 2024-10-08 09:05:04 +0200
• 9ad5d21231
  Merge pull request #2089 from VOGL-electronic/efinix_tristate_fix enjoy-digital 2024-10-07 11:06:26 +0200
• 4fcae9f3c7
  build: efinix: Tristate fix Fin Maaß 2024-10-07 10:15:38 +0200
• 64cf925b39 soc/integration/soc: Cleanup imports and directly use math.log2/ceil since math is already imported. Florent Kermarrec 2024-10-02 17:08:46 +0200
• 5e897752b7 soc/intergration/soc/add_pcie: Add new status_width parameter. Florent Kermarrec 2024-09-27 11:46:19 +0200
• d63d8d99df build: io.py: DDRTristate: check oe2 Fin Maaß 2024-09-18 15:05:46 +0200
• c1733ea2ff build: io: make oe2 of DDRTristate optional Fin Maaß 2024-09-12 09:48:15 +0200
• 644ef7e4e5
  Merge pull request #2086 from VOGL-electronic/build_io_clocksignal enjoy-digital 2024-10-01 11:49:03 +0200
• 280b6b4ee4
  build: io: don't use mutable object as default value Fin Maaß 2024-09-30 15:18:11 +0200
• e4ad995403
  litei2c: add to litex Fin Maaß 2024-09-27 10:27:42 +0200
• 87ee6ec3a0 CHANGES.md: Prepare for post 2024.08 changes. Florent Kermarrec 2024-09-27 09:58:09 +0200
• f72368abaa CHANGES.md: Do 2024.08 release. 2024.08 Florent Kermarrec 2024-09-27 09:45:11 +0200
• 58e916d86e setup.py: 2024.08 release. Florent Kermarrec 2024-09-27 09:37:11 +0200
• 50bb6bb1ff CHANGES.md: Update. Florent Kermarrec 2024-09-27 09:33:22 +0200
• 2130ff2fb3 build/efinix/efinity: Cosmetic cleanup on toolchain arguments. Florent Kermarrec 2024-09-26 18:06:36 +0200
• 1568b25ff7 build/efinix/common: Cosmetic cleanups. Florent Kermarrec 2024-09-26 18:03:36 +0200
• 431feb0ac2 build/efinix/common: Enable back SDRInput since support fixed with recent changes. Florent Kermarrec 2024-09-26 18:01:02 +0200
• 9760493c32 build/efinix/common: Switch to LiteXModule. Florent Kermarrec 2024-09-26 17:46:07 +0200
• 95e5e7302e
  Merge pull request #2083 from VOGL-electronic/efinix_common_improve enjoy-digital 2024-09-26 17:41:07 +0200
• c67dfa82cc
  Merge pull request #2079 from VOGL-electronic/efinix_iface_fixups enjoy-digital 2024-09-26 17:31:53 +0200
• a825c61385 build: efinix: EfinixTristateImpl: use GPIO Bus Fin Maaß 2024-09-26 15:58:29 +0200
• e9a4b178ce build: efinix: platform.py: add get_pins_location and get_pins_name Fin Maaß 2024-09-26 15:53:56 +0200