Charles Papon
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9995c5109d
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move tests
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2017-05-21 16:53:48 +02:00 |
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Charles Papon
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6c1d953647
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DebugPlugin fully implemented
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2017-05-20 18:15:15 +02:00 |
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Charles Papon
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619739d33a
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preliminary DebugPlugin
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2017-05-20 15:16:45 +02:00 |
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Dolu1990
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cabf602efc
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Update README.md
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2017-05-19 17:13:33 +02:00 |
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Charles Papon
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a5364ad001
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Add flush support instruction into the instruction cache
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2017-05-19 11:20:33 +02:00 |
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Charles Papon
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736478ff1d
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CsrPlugin now catch illegal CSR access (wrong address + to low privilege level)
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2017-05-09 00:40:44 +02:00 |
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Charles Papon
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fe184636dd
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Improve CsrPlugin FMax
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2017-05-08 22:59:05 +02:00 |
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Charles Papon
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c69fdf7987
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Add basics of the USER mode to CsrPlugin
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2017-05-07 23:41:54 +02:00 |
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Charles Papon
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579e93bb5a
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Rename MachineCsr plugin into CsrPlugin
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2017-05-07 22:26:17 +02:00 |
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Charles Papon
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392f3a7d8c
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Add PrivilegeService (User) (not implemented)
Split caches from their plugins file
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2017-05-07 20:16:41 +02:00 |
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Charles Papon
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a51c27970b
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Add opcode for clean/invalidate the datacache
Change mmu opcodes
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2017-05-07 16:02:55 +02:00 |
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Charles Papon
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4d6a6fbb02
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Fix Instruction Data cache exceptions
Pass all tests including CSR/FreeRTOS
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2017-05-07 12:51:47 +02:00 |
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Charles Papon
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ca1bc9cf69
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DataCache plugin now support all exceptions
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2017-05-07 10:44:41 +02:00 |
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Charles Papon
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5ba8ab7947
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DataCache add invalidate/clean/invalidateClean on a virtual address/way
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2017-05-05 00:43:41 +02:00 |
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Charles Papon
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48a5dc8e79
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DCache move the exception bus outside the cache component
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2017-05-04 21:01:08 +02:00 |
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Charles Papon
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534a4c3494
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mmu working for instruction and data bus (both tested)
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2017-05-03 18:42:54 +02:00 |
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Charles Papon
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c647ef8bb6
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Rework constructors
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2017-05-01 20:20:21 +02:00 |
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Charles Papon
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889a040f90
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Fix multi port MMU design
Change machineCSR to handle exceptions from the writeBack stage
Change the DBusCachedPlugin to emit miss exception
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2017-05-01 14:29:37 +02:00 |
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Charles Papon
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2ed33106d6
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MMU pass simple regression !
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2017-04-29 19:58:17 +02:00 |
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Charles Papon
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227772f19c
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Add miss files
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2017-04-28 16:41:44 +02:00 |
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Charles Papon
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010ba568f0
|
MMU implemented
Datacached using MMU implemented
It compile, but nothing is tested
|
2017-04-28 16:41:23 +02:00 |
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Charles Papon
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ba2ca77114
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Two stage datacache now pass dhrystone benchmark without error
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2017-04-23 23:15:38 +02:00 |
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Charles Papon
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9040326273
|
WIP two stage DCache, nearly passed the dhrystone benchmark
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2017-04-23 18:31:16 +02:00 |
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Charles Papon
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e00bf028cb
|
Add HazardPessimisticPlugin for light and very good FMAX hazard tracking
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2017-04-17 17:56:47 +02:00 |
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Charles Papon
|
024e14ae58
|
Smaller and faster single stage instruction cache
Add fast two stage instruction cache
Remove useless address == 0 checks in the HazardPlugin
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2017-04-13 18:27:03 +02:00 |
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Charles Papon
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c83a157c64
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IBusCachedPlugin with twoStage config is now compatible with syncronous regfile
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2017-04-09 11:59:09 +02:00 |
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Charles Papon
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9a4c35d7b6
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IBusCachedPlugin twoStage config fix
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2017-04-08 18:34:44 +02:00 |
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Charles Papon
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e3b9e671ec
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IBusCachedPlugin add two stage cache option for better FMax and better scaling
|
2017-04-08 17:42:13 +02:00 |
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Charles Papon
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5c594d6d2a
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IBusCachedPlugin move memory access outside the pipeline
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2017-04-07 13:27:47 +02:00 |
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Charles Papon
|
8f09867bda
|
Cleaning
|
2017-04-07 13:09:31 +02:00 |
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Charles Papon
|
efb27390a7
|
Better IntAluPlugin
Better SrcPlugin
Better DBusCachedPlugin
|
2017-04-06 01:28:52 +02:00 |
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Charles Papon
|
2e02a6f0e7
|
DBusCachedPlugin better write to read hazard logic (FMAX)
Add some TODO FMAX comments
|
2017-04-05 18:37:02 +02:00 |
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Charles Papon
|
179e7f7b4c
|
IBusCachedPlugin add asyncTagMemory option
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2017-04-05 14:25:11 +02:00 |
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Charles Papon
|
2b24cbc8e1
|
Add pessimistic harzard options
Add separated add/sum option in srcPlugin
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2017-04-04 00:25:39 +02:00 |
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Charles Papon
|
acb85a1fb8
|
Add some decoder comments
|
2017-04-03 01:33:54 +02:00 |
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Charles Papon
|
8ff05bd2a8
|
Much better decoder using Quine-Mc Cluskey
|
2017-04-02 21:05:25 +02:00 |
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Charles Papon
|
a9f7177181
|
Data cache pass dhrystone benchmark.
Data cache todo -> bus error handling
|
2017-04-01 17:06:59 +02:00 |
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Charles Papon
|
2f384364d8
|
Data cache WIP
refractoring
|
2017-03-31 15:20:51 +02:00 |
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Charles Papon
|
26597f78cd
|
cleaning
|
2017-03-31 11:06:40 +02:00 |
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Charles Papon
|
19fe998a52
|
Instruction cache is now able to catch bus errors
|
2017-03-30 17:34:24 +02:00 |
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Charles Papon
|
95585b4d9a
|
Add instruction cache plugin (tested)
|
2017-03-30 10:03:53 +02:00 |
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Charles Papon
|
32d32845bd
|
Add tests for iRsp, dRsp access faults
|
2017-03-28 20:25:58 +02:00 |
|
Charles Papon
|
2cb0e90077
|
refractoring/cleaning
|
2017-03-28 01:53:37 +02:00 |
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Charles Papon
|
62a55c4cf4
|
Add IRsp/dRsp ready + error capabilities to stall the bus and to generate access error exceptions
|
2017-03-28 01:24:29 +02:00 |
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Charles Papon
|
eecc1e6b18
|
Add MachineCsr.mbadaddr logics
|
2017-03-27 18:35:27 +02:00 |
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Charles Papon
|
349d600182
|
Better readme
cleaning
|
2017-03-27 00:33:34 +02:00 |
|
Charles Papon
|
e5148e5e05
|
Better readme
|
2017-03-26 22:43:00 +02:00 |
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Charles Papon
|
70e8bc503e
|
Add readme
|
2017-03-26 22:38:07 +02:00 |
|
Charles Papon
|
91c52f4e46
|
Decoder now catch illegal instructions
|
2017-03-26 18:02:48 +02:00 |
|
Charles Papon
|
c5520656e5
|
Now able to catch missaligned instruction/data addresses
Modify arbitration with an flushAll + isFlushed
|
2017-03-26 17:20:07 +02:00 |