Dolu1990
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dda5372a6c
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Fix typo
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2017-12-14 01:05:06 +01:00 |
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Dolu1990
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d6e0761065
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Fix led gui refresh rate
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2017-12-14 01:04:31 +01:00 |
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Dolu1990
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2259c9cb0f
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Add SpinalHDL sim (1.0.0)
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2017-12-14 00:57:12 +01:00 |
Dolu1990
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5a8c131eb5
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Update README.md
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2017-12-13 13:24:43 +01:00 |
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Dolu1990
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5c8251d6a7
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Update README.md
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2017-12-13 13:23:55 +01:00 |
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Dolu1990
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04ca72df66
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Update README.md
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2017-12-05 16:29:26 +01:00 |
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Dolu1990
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f10dabd253
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SpinalHDL 0.11.5 update
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2017-12-05 15:58:05 +01:00 |
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Dolu1990
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e1b86ea511
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SpinalHDL 0.11.4 update
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2017-12-01 11:19:23 +01:00 |
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Dolu1990
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586d3ed286
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Update formal VexRiscv to halt on missaligned dbus
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2017-11-26 15:30:48 +01:00 |
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Dolu1990
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4de0aac469
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Merge branch 'formal'
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2017-11-24 14:03:25 +01:00 |
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Dolu1990
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b7f4f09814
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Update verilator makefiles to support the last SpinalHDL changes (process merges)
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2017-11-21 23:56:46 +01:00 |
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Dolu1990
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9b9bbaa4ad
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Add missing full config for the iBus
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2017-11-21 00:09:02 +01:00 |
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Dolu1990
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ce6fd6d0aa
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Add VexRiscvAxi4 demo
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2017-11-20 23:57:37 +01:00 |
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Dolu1990
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7c19288648
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Update Synthesis bench
Update some synthesis results
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2017-11-17 20:10:46 +01:00 |
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Dolu1990
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635417aec2
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Merge pull request #9 from kaofishy/master
Minor fixes to Murax.scala
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2017-11-16 21:16:53 +01:00 |
Tony Kao
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290dbc106e
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Fixes GPIO width mismatch
Adds explicit type to apbDecoder.slave to suppress IDE errors
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2017-11-16 15:02:13 -05:00 |
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Dolu1990
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9f9ec823b8
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SpinalHDL 0.11.2
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2017-11-15 17:57:08 +01:00 |
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Dolu1990
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6c3fed3505
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SpinalHDL 0.11.1
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2017-11-15 16:44:42 +01:00 |
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Dolu1990
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be3d301eaf
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Merge remote-tracking branch 'origin/spinalhdl_reworkDev'
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2017-11-12 13:08:05 +01:00 |
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Dolu1990
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838c13d68b
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spinal.core.internals literals import
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2017-11-10 13:14:30 +01:00 |
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Dolu1990
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3060296b94
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unsetRegIfNoAssignement -> allowUnsetRegToAvoidLatch
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2017-11-10 11:33:04 +01:00 |
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Dolu1990
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c3a7f4e58c
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CSR unsetRegIfNoAssignement fix
BranchPlugin doesn't emit the prediction cache when the STATIC setup is used
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2017-11-10 00:59:31 +01:00 |
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Dolu1990
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d6777ae8ec
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usetRegIfNoAssign upgrade
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2017-11-09 20:10:56 +01:00 |
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Dolu1990
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a72c7fd0d1
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Clean Murax toplevel by extracting integrated Area into dedicated components located in MuraxUtiles.scala
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2017-11-07 22:19:33 +01:00 |
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Dolu1990
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714d44d248
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Add fixed bug into the FormalPlugin comments
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2017-11-07 13:54:07 +01:00 |
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Dolu1990
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0cf278b04f
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Update README.md
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2017-11-07 00:12:58 +01:00 |
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Dolu1990
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200a73bea0
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Fix FormalPlugin to pass liveness again.
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2017-11-06 23:04:33 +01:00 |
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Dolu1990
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8098a03a9b
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with no bus stall, pass all tests except uniqueness
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2017-11-06 20:26:45 +01:00 |
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Dolu1990
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e2a432eb5e
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add HaltOnExceptionPlugin
wip
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2017-11-05 20:13:27 +01:00 |
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Dolu1990
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276f7895e7
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Add FormalPlugin
Add FormalSimple CPU configuration
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2017-11-04 00:55:32 +01:00 |
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Dolu1990
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ba42f71813
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pass VexRiscv regressions
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2017-10-30 14:29:25 +01:00 |
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Dolu1990
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173336af33
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Update README.md
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2017-10-20 14:44:31 +02:00 |
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Dolu1990
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9d75349d7a
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Merge pull request #6 from plex1/master
updated main.cpp
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2017-10-18 00:17:49 +02:00 |
Ubuntu
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008a5b7309
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updated main.cpp
added missing using namespace std
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2017-10-17 22:09:08 +00:00 |
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Dolu1990
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228623a309
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Update pinsec picture
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2017-10-16 12:06:24 +02:00 |
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Dolu1990
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6f0c792cb8
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Add brieySoc.png image
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2017-10-16 12:02:40 +02:00 |
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Dolu1990
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2bf7ca24f2
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Add VexRiscvAvalonWithIntegratedJtag
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2017-10-16 11:52:17 +02:00 |
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Dolu1990
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8857bcd7f6
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Add documentation about resets
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2017-10-16 11:31:03 +02:00 |
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Dolu1990
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aa859aae6b
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Update framework.h
Add missing using namespace std;
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2017-10-05 10:08:09 +02:00 |
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Dolu1990
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0327c5ec3a
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Update README.md
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2017-08-31 10:09:11 +02:00 |
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Dolu1990
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09ba7c28da
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Change some xx.input(REGFILE_WRITE_DATA) for xx.output(REGFILE_WRITE_DATA)
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2017-08-27 15:21:44 +02:00 |
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Dolu1990
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8168c9bf3a
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Update simd_add makefile
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2017-08-27 14:49:36 +02:00 |
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Dolu1990
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a8191b6092
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Fix sbt version to 0.13.7
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2017-08-17 03:39:52 +02:00 |
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Dolu1990
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d543325294
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script about gcc prebuild version
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2017-08-17 02:46:12 +02:00 |
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Dolu1990
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3db3795e0a
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Update sbteclipse-plugin
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2017-08-17 02:04:25 +02:00 |
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Charles Papon
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7811d90f99
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update gcc path
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2017-08-14 12:16:40 +02:00 |
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Charles Papon
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8fbd777794
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Update readme with GCC changes from the VexRiscvSocSoftware repo
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2017-08-14 11:40:33 +02:00 |
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Charles Papon
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85fa3776d3
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Readme fix typo
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2017-08-11 13:49:27 +02:00 |
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Charles Papon
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2c6889e688
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Murax mainBus now handle unmapped memory access allowing the debug to access unmapped area without locking the CPU
Murax add dhrystone config
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2017-08-10 22:48:00 +02:00 |
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Dolu1990
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6072e9157e
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Update VexRiscv area/Fmax
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2017-08-10 22:13:19 +02:00 |