Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
518 Commits 39 Branches 2 Tags 15 MiB
Commit Graph

518 Commits

Author SHA1 Message Date
Dolu1990 1da055dc34
Merge pull request #49 from cutephoton/avalon 
Avalon: Debug Clock Domain for JTAG
 2018-12-23 16:27:50 +01:00
Brett Foster 961abb3cf1 Avalon: Debug Clock Domain for JTAG 
This change ensures that the clock domain for the JTAG interface
uses the debug plugin's domain. Otherwise, resetting the processor
will put the jtag debugger in to reset as well.

See SpinalHDL/VexRiscv#48
 2018-12-22 07:58:59 -08:00
Dolu1990 6334f430fe
Update README.md 
Fix #44
 2018-12-04 19:07:51 +01:00
Dolu1990 f54865bcb8 Merge remote-tracking branch 'origin/dev' 2018-11-29 22:43:26 +01:00
Dolu1990 2f6a2dfccc Add configs setup in SimpleBusInterconnect 2018-11-29 16:14:45 +01:00
Dolu1990 7075e08d9f Hazarplugin tell to branch plugin if the RS are hazardous in the execute stage 2018-11-24 13:38:54 +01:00
Dolu1990 c2b9544794 Allow iBusCached plugin to be used when no memory stage is present 2018-11-24 13:37:53 +01:00
Dolu1990 2d8d3d0566 Update readme 2018-11-22 22:49:16 +01:00
Dolu1990 f18696357f SpinalHDL 1.2.2 2018-11-22 22:45:07 +01:00
Dolu1990 0086de9e36 Fix CsrPlugin catch illegalAccess 
Add dhrystone optimized divider
cleaning
 2018-11-20 19:39:17 +01:00
Dolu1990 75d4d049d7 Add shadow regfile 
various cleaning
 2018-11-16 17:06:11 +01:00
Dolu1990 cc48fc7403 add fenceiGenAsANop 2018-11-13 15:17:35 +01:00
Dolu1990 0d92a5e5cd Add many little options to reduce area 2018-11-12 14:14:34 +01:00
Dolu1990 fb9ea11a5e Allow VexRiscv to suppress the memory and the writeback stage, allowing to go downto a 2 stage CPU (FETCH_DECODE, EXECUTE) 2018-11-09 05:41:43 +01:00
Dolu1990 b12e15b112 branch/csr/muldiv minor improvments 2018-11-07 19:27:49 +01:00
Dolu1990 b7f3ee5e06 Fix CsrPlugin pipelined option 2018-11-05 16:22:41 +01:00
Dolu1990 662d76e3aa csrPlugin : avoid using ALU to get SRC1 (which was useless) 2018-11-03 11:29:30 +01:00
Dolu1990 978232fd63 Optimise div iterative plugin done signal 2018-11-03 11:12:37 +01:00
Dolu1990 c8ac214097 Optimize CSR 2018-10-28 02:18:27 +02:00
Dolu1990 51de2b5820 SimpleBusInterconnect now adapte address width 2018-10-28 02:18:08 +02:00
Dolu1990 00bf84b7f8 Add SimpleBusInterconnect 2018-10-25 23:47:05 +02:00
Dolu1990 4ed4af6a3e SrcPlugin add decodeAddSub option 2018-10-24 01:28:37 +02:00
Dolu1990 372063582c Improve CsrPlugin CombinatorialPaths 2018-10-23 19:07:08 +02:00
Dolu1990 7096c63d50 Add more SimpleBus utilies 2018-10-23 17:46:31 +02:00
Dolu1990 7c0f2dc713 Add SimpleBus object 2018-10-20 12:39:30 +02:00
Morard Dany 85e696b286 CsrPlugin : Add mtvecModeGen 2018-10-16 14:53:41 +02:00
Dolu1990 1e64d71609 Merge remote-tracking branch 'origin/Supervisor' into dev 2018-10-16 13:09:17 +02:00
Dolu1990 905abd5aaa Add wfiGenAsWait and wfiGenAsNop 
CsrPlugin cleaning
Much cleaning in general
Zephyr is running
 2018-10-16 13:07:30 +02:00
Dolu1990 25c0a0ff6f
Add RVC into the readme 
Forgot to add RVC (compressed) support information into the readme
 2018-10-13 09:57:13 +02:00
Dolu1990 f903df4b66 sync 2018-10-12 17:13:54 +02:00
Dolu1990 2b29690010 Clean branch plugin lsb bit calculation 
BranchPlugin doesn't try anymore to catch exception when RVC is on
 2018-10-12 12:24:52 +02:00
Dolu1990 eea92154ae fetcher force PC LSB to be zero 2018-10-12 12:02:52 +02:00
Dolu1990 0b8f6f6ed4 Fix broken C.LWSP reference_output 2018-10-12 12:02:02 +02:00
Dolu1990 594f7a8bf2 Seem to pass all risc-v compliance tests, excepted the C.LWSP which is a broken test 2018-10-11 22:19:17 +02:00
Dolu1990 8c25e73b9d Fix DIV negative values divided by zero 2018-10-11 22:18:21 +02:00
Dolu1990 c26b7e15cf BranchPlugin exceptions are now risc-v compliance alligned 2018-10-11 17:56:49 +02:00
Dolu1990 8b1a4a2717 Add RISCV compliance regression test, need to fix I-MISALIGN_JMP-01 mtval 2018-10-11 00:25:39 +02:00
Dolu1990 40d85b8c70 Add fenceiGenAsAJump into BranchPlugin 2018-10-10 21:13:21 +02:00
Dolu1990 68f1ff3222 Add CsrPlugin ebreak support 2018-10-10 19:23:04 +02:00
Dolu1990 0662cc2797 Add GenMicro experiment to reduce ice40 area usage. 
IBusSimplePlugin now require cmdFork parameters to be set (no default)
 2018-10-03 22:08:57 +02:00
Dolu1990 48bff80653 rework fetchPc to optionaly share the pcReg with the stage(1) 
IBusSimplePlugin now implement cmdForkPersistence option
 2018-10-03 16:24:10 +02:00
Dolu1990 c61f17aea3 Fetcher/IBusSimplePlugin wip 2018-10-03 01:02:22 +02:00
Dolu1990 0ada869b2d regression golden ref regfile is now sync with trl boot's random values 
wip
 2018-10-01 16:14:21 +02:00
Dolu1990 65a8d84d30 Introduce HAS_SIDE_EFFECT Stageable to solve sensitive instruction squeduling 
(uncached DBus TODO)
 2018-10-01 12:13:05 +02:00
Dolu1990 7770eefa3b wip 2018-09-30 12:57:08 +02:00
Dolu1990 39c6bc11d6 Pass basic regression again 2018-09-29 19:04:20 +02:00
Dolu1990 5ad7c39f47 wip 2018-09-29 12:04:58 +02:00
Dolu1990 37a1970ad6 wip 2018-09-28 16:02:33 +02:00
Dolu1990 32cf90a162 Merge remote-tracking branch 'origin/dev' into Supervisor 2018-09-27 22:16:49 +02:00
Dolu1990 992c21ddd1 fix travis 2018-09-27 19:06:33 +02:00