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VexRiscv
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792 Commits

Author SHA1 Message Date
Charles Papon 310c325eaa IBusCached add Keep attribut on the line loader to avoid Artix7 block ram merge, but do not seem to have effect 2019-10-11 00:24:21 +02:00
Charles Papon 711eed1e77 MulPlugin add withInputBuffer feature and now use RSx instead of SRCx 2019-10-11 00:23:29 +02:00
Charles Papon 3fc0a74102 Add Keep attribut on dBusCached relaxedMemoryTranslationRegister feature 2019-10-11 00:22:44 +02:00
Charles Papon 51d22d4a8c Merge remote-tracking branch 'origin/cfu' into dev 2019-10-10 15:00:43 +02:00
Charles Papon 6ed41f7361 Improve CSR FMax 2019-09-16 13:53:55 +02:00
Charles Papon d94cee13f0 Add dummy decoding, exception code/tval 
Add Cpu generation code
Add support for always ready rsp
 2019-09-05 19:06:28 +02:00
Charles Papon 5ac443b745 Manage cases where a rsp buffer is required 2019-09-05 10:41:45 +02:00
Dolu1990 6951f5b8e6 CfuPlugin addition 2019-09-05 10:41:45 +02:00
Dolu1990 84602f89b0 Merge pull request #80 from antmicro/fix_litex_target 
Fix handling LiteX uart and timer.
 2019-09-05 10:41:45 +02:00
Dolu1990 0efcaa505d Merge pull request #79 from antmicro/litex_target 
Litex target
 2019-09-05 10:41:45 +02:00
Mateusz Holenko 86f5af5ca9 Fix handling LiteX uart and timer. 2019-09-05 10:41:45 +02:00
Charles Papon 94f1707d65 Merge branch 'dev' 2019-09-05 10:41:45 +02:00
Mateusz Holenko 8813e071bc Add `litex` target 
Use configuration from the `csr.h` file
generated dynamically when building a LiteX platform.
 2019-09-05 10:41:45 +02:00
Mateusz Holenko 64a2815544 Create makefile targets 
Allow to change build target without modifiying the sources.
In order to keep compatibilty `sim` target is built by default.
 2019-09-05 10:41:45 +02:00
Mateusz Holenko e76435c6c6 Allow to set custom DTB/OS_CALL addresses 
Setting those from command line during compilation allows
to create a custom setup without the need of modifying the
sources.
 2019-09-05 10:41:45 +02:00
Mateusz Holenko c8280a9a88 Allow to set custom RAM base address for emulator 
This is needed when loading the emulator to RAM
with an offset.
 2019-09-05 10:41:45 +02:00
Charles Papon b65ef189eb sync with SpinalHDL SDRAM changes 2019-08-29 16:03:20 +02:00
Charles Papon a2569e76c0 Update sdram ctrl package 2019-07-08 11:23:48 +02:00
Charles Papon 624c641af5 xip refractoring 2019-06-28 10:23:39 +02:00
Charles Papon b2e06ae198 Back into unreleased SpinalHDL 2019-06-17 17:19:11 +02:00
Charles Papon 1257b056dc Revert "test only dynamic_target for intensive test" 
This reverts commit 635ef51f82.
 2019-06-16 18:24:59 +02:00
Charles Papon 12c3ab16ae Update readme perf 2019-06-16 18:07:04 +02:00
Charles Papon 635ef51f82 test only dynamic_target for intensive test 2019-06-16 17:43:07 +02:00
Charles Papon 9656604848 rework dynamic_target failure correction 2019-06-16 17:42:39 +02:00
Charles Papon 4cf7e5b98f SpinalHDL 1.3.6 2019-06-16 00:42:59 +02:00
Charles Papon 60c9c094a7 Merge remote-tracking branch 'origin/rework_jump_flush' into dev 2019-06-15 18:09:38 +02:00
Charles Papon 46e9d5566a Merge branch 'rework_jump_flush' 2019-06-15 18:05:04 +02:00
Charles Papon 7c3c4e8c81 Update readme benches 2019-06-15 14:23:09 +02:00
Charles Papon a3a0c402bc Remove broken freertos test and add zephyr instead 2019-06-15 10:46:10 +02:00
Charles Papon 617f4742cd Fix dynamic branch prediction correction on misspredicted fetch which are done on a 32 bits instruction crossing two words in configs which have at least 2 cycle latency fetch 2019-06-14 08:13:22 +02:00
Charles Papon d603de1bfe Fix recent changes 2019-06-13 16:55:24 +02:00
Charles Papon c8ab99cd0b Cleaning and remove BlockQ regression 2019-06-12 00:00:38 +02:00
Charles Papon 21ec368927 Fix DYNAMIC_TARGET by fixing decode PC updates 2019-06-11 19:56:33 +02:00
Charles Papon afbf0ea777 Fix regression makefile 2019-06-11 01:05:49 +02:00
Charles Papon 066ddc23e6 Add regression concurrent os executions flag to avoid running debug plugin tests 2019-06-11 00:22:38 +02:00
Charles Papon 21c8933bbb Fix DYNAMIC_TARGET prediction correction in BranchPlugin 2019-06-11 00:12:29 +02:00
Charles Papon 5b53440d27 DYNAMIC_TARGET prediction datapath/control path are now splited 2019-06-10 22:20:32 +02:00
Charles Papon 0e95154869 individual regression : more env control 2019-06-10 21:01:41 +02:00
Charles Papon bd46dd88aa Fix RVC fetcher pc branches 2019-06-10 20:48:04 +02:00
Charles Papon 24e1e3018c Fix exception handeling 2019-06-09 23:40:37 +02:00
Charles Papon 5243e46ffb Fix BranchPlugin when SRC can have hazard in execute stage 2019-06-09 20:15:36 +02:00
Charles Papon af0755d8cf rework flush with flushNext and flushIt 
static branch prediction jump do not depend on stage fireing anymore
 2019-06-09 15:44:05 +02:00
Charles Papon 0e2d40c37f Merge remote-tracking branch 'origin/pipelinedInterrupt' 2019-06-09 12:29:20 +02:00
Charles Papon 357681a5c6 csrPlugin add pipelinedInterrupt, set by default 2019-06-08 22:22:16 +02:00
Charles Papon 0df4ec45ad Merge remote-tracking branch 'origin/master' into dev 
# Conflicts:
#	build.sbt
 2019-06-05 00:35:41 +02:00
Charles Papon 56f7c27d18 Fix WFI. Not sensitive anymore to global interrupt enables, delegation and privilege 2019-06-05 00:32:38 +02:00
Dolu1990 64e8919e89
Update README.md 
Add litex repo
 2019-05-28 11:28:07 +02:00
Charles Papon 38a464a829 DataCache now allocate ways randomly 2019-05-25 00:28:30 +02:00
Charles Papon 4a40184b35 Add cache Bandwidth counter, previous commit was about random instruction cache way allocation 2019-05-25 00:22:27 +02:00
Charles Papon 94606d38e2 Add cache bandwidth counter 2019-05-25 00:21:48 +02:00