Dolu1990
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3ba509931c
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Add VexRiscvSmpLitexCluster with the required pipelining to get proper FMax
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2020-04-27 17:38:06 +02:00 |
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Dolu1990
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5fd0b220cd
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CsrPlugin add openSbi config
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2020-04-27 17:37:30 +02:00 |
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Dolu1990
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0c59dd9ed3
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SMP fence now ensure ordering for all kinds of memory transfers
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2020-04-27 17:37:15 +02:00 |
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Dolu1990
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3fb123a64a
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fix withStall
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2020-04-21 21:20:54 +02:00 |
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Dolu1990
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3885e52bb7
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Merge remote-tracking branch 'origin/dev' into smp
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2020-04-21 17:21:48 +02:00 |
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Dolu1990
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4016b1fc52
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Add sbt assembly
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2020-04-21 17:18:08 +02:00 |
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Dolu1990
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056bf63866
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Add more consistancy tests
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2020-04-21 16:03:03 +02:00 |
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Dolu1990
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b389878d23
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Add smp consistency check, fix VexRiscv invalidation read during write hazard logic
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2020-04-21 12:18:10 +02:00 |
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Dolu1990
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0e55caacab
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deduplicae VexRiscv wishbone
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2020-04-21 10:33:51 +02:00 |
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Dolu1990
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b383b4b98b
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Add commented usage of fromXilinxBscane2
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2020-04-20 12:13:12 +02:00 |
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Dolu1990
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8e8b64feaa
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Got full linux / buildroot to boot in 4 cpu config
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2020-04-19 19:49:26 +02:00 |
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Dolu1990
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a1b6353d6b
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workaround AMO LR/SC consistancy issue, but that need a proper fix
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2020-04-19 19:48:57 +02:00 |
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Dolu1990
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ad2d2e411a
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Add tap less debug plugin bridges
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2020-04-19 17:56:33 +02:00 |
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Dolu1990
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af128ec9eb
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revert to 4 cpu
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2020-04-18 01:27:35 +02:00 |
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Dolu1990
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4a49e6d91f
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initialize the clint in sim
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2020-04-18 01:26:31 +02:00 |
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Dolu1990
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befecc7ed6
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cleaning
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2020-04-18 00:51:57 +02:00 |
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Dolu1990
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8c0e534c6b
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Add openSBI test, seem to work fine
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2020-04-18 00:51:47 +02:00 |
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Dolu1990
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ebe070f9dd
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Update README.md
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2020-04-17 19:58:54 +02:00 |
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Dolu1990
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d5a52caab8
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fix smp test barrier
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2020-04-16 17:27:27 +02:00 |
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Dolu1990
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d88d04dbc4
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More SMP tests (barrier via AMO and LRSC)
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2020-04-16 15:23:25 +02:00 |
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Dolu1990
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fd52f9ba50
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Add smp.bin
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2020-04-16 02:22:18 +02:00 |
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Dolu1990
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73c21177e5
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Add VexRiscvSmpCluster, seem to work on simple case
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2020-04-16 01:30:03 +02:00 |
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Dolu1990
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b9ceabf128
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few fixes
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2020-04-16 01:29:13 +02:00 |
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Dolu1990
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46207abbc4
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dataCache now implement invalidation sync
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2020-04-16 01:28:38 +02:00 |
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Dolu1990
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a00605b10c
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fix Briey verilator
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2020-04-13 13:01:12 +02:00 |
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Dolu1990
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467a2bc488
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refactor DBus invalidation, and add invalidation enable
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2020-04-11 19:06:22 +02:00 |
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Dolu1990
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abbfaf6bcf
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regression : restore normal invalidation setup
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2020-04-10 18:58:03 +02:00 |
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Dolu1990
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4a9b8c1f72
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improve invalidation read during write hazard logic
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2020-04-10 14:44:28 +02:00 |
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Dolu1990
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0ad0f5ed3f
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Add d$ invalidation tests
fix d$ invalidation, linux OK
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2020-04-10 14:28:16 +02:00 |
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Dolu1990
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f71f360e32
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Add SMP synthesis
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2020-04-10 14:27:39 +02:00 |
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Dolu1990
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296cb44bc4
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Add hardware AMO support using LR/SC exclusive
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2020-04-09 20:12:37 +02:00 |
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Dolu1990
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1d0e180e1d
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Add GenTwoStage config and UltraScale synthesis
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2020-04-09 20:11:56 +02:00 |
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Dolu1990
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861df664cf
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clean some AMO stuff
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2020-04-08 18:48:01 +02:00 |
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Dolu1990
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6922f80a87
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DataCache now implement fence operations
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2020-04-08 18:12:13 +02:00 |
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Dolu1990
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9e1817a280
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fix DataCache for config without invalidation
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2020-04-07 20:05:24 +02:00 |
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Dolu1990
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0c8ea4a368
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DataCache add invalidation feature
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2020-04-07 19:18:20 +02:00 |
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Dolu1990
|
1ef099e308
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Merge branch 'dev' into smp
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2020-04-07 12:29:58 +02:00 |
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Dolu1990
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5eaa5ba4db
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Update README.md
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2020-04-07 12:29:40 +02:00 |
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Dolu1990
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6e239fb280
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Update README.md
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2020-04-07 12:29:40 +02:00 |
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Dolu1990
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f20eb4d541
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Merge pull request #115 from antmicro/fix_emulator
emulator: Use external hw/common.h from LiteX
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2020-04-07 12:29:40 +02:00 |
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Dolu1990
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ddc59bc404
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Fix DebugPlugin step by step
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2020-04-07 12:27:52 +02:00 |
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Dolu1990
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5aa0b86d96
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Fix DebugPlugin step by step
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2020-04-07 12:13:40 +02:00 |
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Dolu1990
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a52b833727
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fix weird regression testbench memory bug
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2020-04-06 21:42:44 +02:00 |
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Dolu1990
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a107e45116
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fix non smp regression
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2020-04-06 06:43:28 +02:00 |
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Dolu1990
|
ca72a421be
|
LrSc align software model to the hardware. Linux OK
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2020-04-05 21:45:45 +02:00 |
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Dolu1990
|
2eec18de65
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LrSc SMP, linux crash in userspace
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2020-04-05 16:28:46 +02:00 |
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Dolu1990
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f2ef8e95ab
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Implement external LrSc
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2020-04-05 11:38:57 +02:00 |
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Dolu1990
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ff074459ad
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Fix LrSc for configs without mmu
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2020-04-04 22:54:35 +02:00 |
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Dolu1990
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c9bbf0d12a
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update LrSc reservation logic to match the spec
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2020-04-04 21:21:35 +02:00 |
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Dolu1990
|
31d2aaa05b
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Update README.md
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2020-03-28 15:38:32 +01:00 |