Dolu1990
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54581f6d9e
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Fix #117 DataCache mem blackboxing
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2020-03-02 14:23:59 +01:00 |
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Dolu1990
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78d4660282
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Merge branch 'dev' into rework_fetch
# Conflicts:
# src/test/scala/vexriscv/TestIndividualFeatures.scala
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2020-03-01 22:58:25 +01:00 |
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Dolu1990
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ea5464ea26
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TestIndividualFeatures is now multithreaded
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2020-03-01 21:40:53 +01:00 |
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Dolu1990
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02545b9bea
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typo
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2020-03-01 13:03:40 +01:00 |
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Dolu1990
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559260020b
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Improve testing infrastructure with more options and better readme
https://github.com/litex-hub/linux-on-litex-vexriscv/issues/112
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2020-03-01 13:02:08 +01:00 |
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Charles Papon
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25d880f6c7
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Fix synthesis bench
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2020-02-28 18:20:08 +01:00 |
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Charles Papon
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c94d8f1c6c
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Fetcher and IBusSimplePlugin flush reworked
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2020-02-28 17:23:44 +01:00 |
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Charles Papon
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492310e6fa
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DBusCachedPlugin fix noWriteBack redo priority
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2020-02-28 17:21:59 +01:00 |
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Charles Papon
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76d063f20a
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Fix MulPlugin keep attribute
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2020-02-24 22:43:08 +01:00 |
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Charles Papon
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999a868c14
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Update readme VexRiscv perf numbers
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2020-02-24 00:07:14 +01:00 |
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Charles Papon
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485b4a5838
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Improve maxPerf configs
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2020-02-23 23:52:43 +01:00 |
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Charles Papon
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fad09e805f
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Add Fetcher.predictionBuffer option to pipeline BRANCH_TARGET, higher FMax, about 1 ns critical path gain on Arty7 => 5 ns
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2020-02-23 23:18:27 +01:00 |
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Charles Papon
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67d2071a32
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typo
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2020-02-23 23:17:02 +01:00 |
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Charles Papon
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c8016e90a4
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MulPlugin now add KEEP attribute on RS1 and RS2 to force Vivado to not retime it with the DSP
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2020-02-23 20:25:31 +01:00 |
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Charles Papon
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01e5112680
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Fetcher RVC ensure redo keep PC(1)
Fix BranchTarget RVC inibition
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2020-02-23 10:44:44 +01:00 |
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Charles Papon
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5ea0b57d1b
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Fix BRANCH_TARGET with RVC patch
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2020-02-22 11:53:47 +01:00 |
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Charles Papon
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41008551c1
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CsrPlugin redo interface do not need next pc calculation
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2020-02-21 20:01:35 +01:00 |
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Charles Papon
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4ad1215873
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Fix iBusSimplePlugin MMU integration
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2020-02-21 13:28:42 +01:00 |
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Charles Papon
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befc54a444
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No more Fetcher flush() API as it can now be done via the decoder.flushNext
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2020-02-21 13:28:29 +01:00 |
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Charles Papon
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32fade50e5
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Fix fetcher decompressor when driving decode stage
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2020-02-21 02:03:29 +01:00 |
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Charles Papon
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59508d5b57
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Fix target branch prediction for RVC, all default configs pass dhrystone
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2020-02-20 02:27:57 +01:00 |
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Charles Papon
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a684d5e4d1
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Rework/clean decompressor logic
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2020-02-19 01:20:52 +01:00 |
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Charles Papon
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a7440426fd
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Fix FetchPlugin redo gen condition
Fix injectorFailure reset
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2020-02-18 01:00:11 +01:00 |
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Charles Papon
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f63c4db469
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Fix CsrPlugin pipeline liberator
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2020-02-18 00:59:39 +01:00 |
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Charles Papon
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53a29e35e9
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fix deleg external interrupt propagation time failure
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2020-02-17 23:27:17 +01:00 |
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Charles Papon
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e0cd9a6e06
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clean iBusRsp redo
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2020-02-17 22:45:34 +01:00 |
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Charles Papon
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0e0a568743
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Apply DYNAMIC_TARGET correction all the time
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2020-02-17 21:43:02 +01:00 |
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Charles Papon
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e23295f06e
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Fix Fetcher pcValid pipeline
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2020-02-17 19:29:41 +01:00 |
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Charles Papon
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9e75e2cb58
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IBusFetcher disable pcRegReusedForSecondStage when using fetch prediction.
Fix some fetch flush
DYNAMIC_PREDICTION start to work again
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2020-02-17 14:36:08 +01:00 |
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Charles Papon
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8be50b8e3d
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IBusFetcher now support proper iBusRsp.redo/flush
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2020-02-17 12:50:12 +01:00 |
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Charles Papon
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ebfa9e6577
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Merge branch 'dev' into rework_fetch
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2020-02-16 18:52:31 +01:00 |
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Charles Papon
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29f85a7ae2
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Remove INSTRUCTION_READY
Add proper Fetcher.ibusRsp.flush
prediction are disabled yet
much is broken for sure, WIP
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2020-02-16 18:44:10 +01:00 |
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Charles Papon
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0c255e2404
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Merge branch 'compiler_plugin' into dev
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2020-02-16 14:34:26 +01:00 |
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Charles Papon
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3d34d754a9
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Remove usages of implicit string to B/U/S
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2020-02-15 10:11:00 +01:00 |
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Charles Papon
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d241f35625
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Remove usages of implicit string to B/U/S
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2020-02-15 10:10:04 +01:00 |
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Charles Papon
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f1959ff830
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smp spec typo
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2020-02-15 00:26:11 +01:00 |
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Charles Papon
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6edab1eb34
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Add SMP spec draft
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2020-02-15 00:24:33 +01:00 |
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Charles Papon
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10da093422
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Fix sbt
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2020-02-06 21:07:40 +01:00 |
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Charles Papon
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38a573a48c
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Update build.sbt
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2020-02-03 13:35:55 +01:00 |
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Charles Papon
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5b8febb977
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Revert "Revert "Merge branch 'master' into dev""
This reverts commit c01c256757.
Fix dBusCachedPlugin relaxedMemoryTranslationRegister when mmu translation is done in the execute stage
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2020-01-29 22:37:09 +01:00 |
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Charles Papon
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c01c256757
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Revert "Merge branch 'master' into dev"
This reverts commit b5374433a5, reversing
changes made to f01da9c73b.
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2020-01-29 15:20:13 +01:00 |
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Charles Papon
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b5374433a5
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Merge branch 'master' into dev
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2020-01-29 12:50:41 +01:00 |
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Dolu1990
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ac79cc6fe6
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Merge pull request #109 from sebastien-riou/arty
missing tcl files for Murax on Arty
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2020-01-17 12:07:54 +01:00 |
sebastien-riou
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badc38d645
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Merge remote-tracking branch 'origin/master' into arty
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2020-01-17 00:54:19 +01:00 |
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sebastien-riou
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1fb1e358bb
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fix makefile clean target
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2020-01-17 00:49:35 +01:00 |
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sebastien-riou
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2bcddd333d
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forced the commit of missing TCL files
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2020-01-17 00:33:02 +01:00 |
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Dolu1990
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95ec47e5b8
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Merge pull request #108 from sebastien-riou/arty
Murax on Arty A7-35
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2020-01-16 23:21:29 +01:00 |
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sebastien-riou
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97b2838d18
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Murax on Digilent Arty A7-35
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2020-01-16 21:58:55 +01:00 |
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sebastien-riou
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195318b665
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Merge pull request #1 from sebastien-riou/VXIP
Murax_xip: better pin names in scala, bootloader without magic word
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2020-01-13 22:06:31 +01:00 |
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sebastien-riou
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de9f704de2
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better pin names in scala, bootloader without magic word
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2020-01-13 21:58:08 +01:00 |