Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
1,207 Commits 39 Branches 2 Tags 15 MiB
Commit Graph

1207 Commits

Author SHA1 Message Date
Samuel Lindemer 7d699dcc13 Remove PMP from MachineOs test defaults 2020-12-10 09:42:27 +01:00
Samuel Lindemer f2ce2eab00 PMP plugin passes regression tests 2020-12-07 12:04:45 +01:00
Samuel Lindemer 763eebeeba Add TOR support, tests pass on GenZephyr 2020-12-04 17:13:31 +01:00
Samuel Lindemer 5cb5061d9b PMP passes test with GenZephyr, but pipeline flushes have been disabled 2020-12-03 17:29:31 +01:00
Dolu1990 9a6931a54c CfuPlugin improve writeback buffering 2020-12-03 16:21:52 +01:00
Samuel Lindemer 987de8fb6a Lock PMP address registers in golden model 2020-12-02 14:18:17 +01:00
Samuel Lindemer 14c39a0070 Merge remote-tracking branch 'upstream/master' into pmp 2020-12-02 14:08:32 +01:00
Samuel Lindemer 872aa19d83 Add PMP to golden model 2020-12-02 12:27:26 +01:00
Samuel Lindemer d5b1a8f565 Add PMP test to regression suite 2020-12-01 18:38:06 +01:00
Dolu1990 45ff78d068 VexRiscvSmpClusterGen.dBusCmdMasterPipe option added 2020-12-01 13:51:10 +01:00
Samuel Lindemer c5023ad973 Add PMP regression test 2020-12-01 09:10:24 +01:00
Dolu1990 1b65a9e523
remove libts-dev from readme 2020-11-30 16:11:00 +01:00
Samuel Lindemer 2d0ebf1ef5 Flush pipeline after PMP CSR writes 2020-11-25 15:38:34 +01:00
Dolu1990 e0ae46e794 Fix Csr ReadWrite interration with DBusCachedPlugin execute halt 
# Conflicts:
#	src/main/scala/vexriscv/plugin/CsrPlugin.scala
 2020-11-18 14:43:24 +01:00
Dolu1990 832218dbec DBusCachedPlugin increase pendingMax to 64 to hide memory latency when saving a full context 2020-11-16 12:38:29 +01:00
Dolu1990 ba523c627a Fix Csr ReadWrite interration with DBusCachedPlugin execute halt 2020-11-16 12:37:48 +01:00
Dolu1990 dae633aa7d
Merge pull request #150 from banahogg/patch-1 
Update GCC prebuild instructions for sifive.com reorg
 2020-11-15 11:25:50 +01:00
banahogg d1691e9478
Update GCC prebuild instructions for sifive.com reorg 2020-11-14 17:31:50 -08:00
Dolu1990 c1b0869c21 AesPlugin is now little endian 2020-11-12 15:07:27 +01:00
Dolu1990 1b2a2ebaca DBusCachedPlugin miss decoded aquire fix 2020-11-12 15:07:07 +01:00
Dolu1990 05e725174c AesPlugin added, work with dropbear encryption, seem ok for decryption (barmetal) 2020-11-02 17:14:52 +01:00
Dolu1990 9abe19317d RegFilePlugin.x0Init do less assumption on other plugin behaviour 2020-11-02 17:01:17 +01:00
Samuel Lindemer 97fe279f7b Enable PMP register lock 2020-10-29 13:37:21 +01:00
Dolu1990 dc9246715d Do not allow jtag ebreak outside machine mode 2020-10-28 13:00:16 +01:00
Dolu1990 4209dc2792 Fix CsrPlugin privilege crossing 2020-10-28 13:00:15 +01:00
Dolu1990 576e21d75d Do not allow jtag ebreak outside machine mode 2020-10-28 12:58:24 +01:00
Dolu1990 abebeaea1f Fix CsrPlugin privilege crossing 2020-10-28 12:57:20 +01:00
Samuel Lindemer fc2c8a7c37 Initial commit of PMP plugin 2020-10-27 09:38:58 +01:00
Dolu1990 fe342c347c CfuBusParameter has now a few default values 2020-10-23 11:06:24 +02:00
Dolu1990 d490f903ea
Merge pull request #145 from zeldin/bigendian2 
Update big endian instruction encoding
 2020-10-21 12:56:56 +02:00
Marcus Comstedt 6c8e97f825 Update big endian instruction encoding 
Between draft-20181101-ebe1ca4 and draft-20190622-6993896 of the
RISC-V Instruction Set Manual, the wording was changed from requiring
"natural endianness" of instruction parcels to require them to be
little endian.

Update the big endian instruction pipe to reflect the newer requirement.
 2020-10-20 18:05:31 +02:00
Dolu1990 4ece59385d DataCache split redo / refilling execute stage halt 2020-10-19 18:12:20 +02:00
Dolu1990 e58daee088 SpinalHDL++ 2020-10-16 11:25:25 +02:00
Dolu1990 ec55187033 improve LightShifterPlugin arbitration halt timings 2020-10-09 11:37:48 +02:00
Dolu1990 bbaa0520c0
Fix UserInterruptPlugin interrupt enable 2020-10-09 10:45:23 +02:00
Dolu1990 8bd1785233
Merge pull request #141 from betrusted-io/dev-asid 
Dev asid
 2020-10-04 15:20:02 +02:00
bunnie 72f85ef6c0 Merge remote-tracking branch 'origin/dev' into dev-asid 2020-10-04 19:53:29 +08:00
Dolu1990 b7e7faebad sbt update 2020-10-04 09:57:34 +02:00
bunnie 65e6f6054b Add ASID field to SATP 
ASID field is missing from the SATP which causes compatibility
issues with Xous.

While this patch resolves the Xous issue, it has not been tested
on Linux.
 2020-10-04 15:34:58 +08:00
Dolu1990 98de02051e
Merge pull request #135 from zeldin/bigendian 
Add support for big endian byte ordering
 2020-10-01 16:43:00 +02:00
Dolu1990 9d35e75fb5
Update README.md 2020-10-01 16:41:24 +02:00
Dolu1990 3f5e771a5c dbus mmu access improvement 2020-09-17 22:06:29 +02:00
Dolu1990 de820daf74 add earlyBranch option to Smp config 2020-09-13 18:33:06 +02:00
Dolu1990 49488d19af pipeline data cache unaligned access check 2020-09-07 12:01:11 +02:00
Dolu1990 775b336ee0
Merge pull request #136 from zeldin/rv32e 
Add support for RV32E in RegFilePlugin
 2020-09-06 22:23:24 +02:00
Marcus Comstedt 8e466dd13c Add support for RV32E in RegFilePlugin 
The RV32E extension removes registers x16-x31 from the ISA.  This
is useful when compiling with -mem2reg to save on BRAMs.  On iCE40
HX8K this option saves 1285 LC:s, which also improves the routing
situation, when using -mem2reg.

Note that the illegal instruction exception required by the RV32E
specification for accesses to registers x16-x31 is not implemented.
 2020-09-06 17:05:31 +02:00
Dolu1990 4c3cad97d3 fix CfuPlugin generation 2020-09-04 10:36:12 +02:00
Marcus Comstedt c489143442 Add support for big endian byte ordering 2020-08-30 15:17:09 +02:00
Dolu1990 7dcaa0c390 VexRiscvSmpCluster now avoid useless decoder for plic/clint 2020-08-13 11:26:11 +02:00
Dolu1990 69d5ba239a Smp config now initialise regfile using logic 2020-07-28 16:15:17 +02:00