Dolu1990
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02b5b9b05c
|
fpu load subnormal and i2f now use single cycle shifter
|
2021-02-03 16:48:09 +01:00 |
|
Dolu1990
|
8e7e736e3e
|
Merge branch 'dev' into fpu
# Conflicts:
# src/main/scala/vexriscv/Riscv.scala
# src/main/scala/vexriscv/ip/fpu/FpuCore.scala
# src/main/scala/vexriscv/ip/fpu/Interface.scala
# src/test/scala/vexriscv/ip/fpu/FpuTest.scala
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2021-02-03 16:06:17 +01:00 |
|
Dolu1990
|
8eb8356dea
|
fpu wip
|
2021-02-03 14:28:02 +01:00 |
|
Dolu1990
|
1d0eecdcb0
|
fpu f2i rounding ok and full shifter
|
2021-02-03 14:27:52 +01:00 |
|
Dolu1990
|
ef011fa0d4
|
fpu moved 1 bit from round to mantissa
|
2021-02-02 11:29:35 +01:00 |
|
Dolu1990
|
a87cb202b1
|
fpu i2f rounding ok
|
2021-02-01 16:12:38 +01:00 |
|
Dolu1990
|
d92adfbad0
|
SpinalHDL version++
|
2021-02-01 15:20:57 +01:00 |
|
Dolu1990
|
6ee45a1014
|
SpinalHDL version++
|
2021-02-01 12:28:33 +01:00 |
|
Dolu1990
|
36b3cd9188
|
Merge branch 'dev'
|
2021-02-01 12:19:21 +01:00 |
|
Dolu1990
|
98eaeaabc8
|
fix regression.mk typo
|
2021-01-30 22:34:54 -01:00 |
|
Dolu1990
|
6aa6191240
|
Merge branch 'master' into dev
# Conflicts:
# build.sbt
# src/main/scala/vexriscv/Riscv.scala
# src/main/scala/vexriscv/ip/DataCache.scala
# src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
# src/main/scala/vexriscv/plugin/MmuPlugin.scala
# src/test/cpp/regression/makefile
# src/test/scala/vexriscv/TestIndividualFeatures.scala
|
2021-01-30 20:30:21 +01:00 |
|
Dolu1990
|
c51b0fcafe
|
fpu mul now pass all roundings
|
2021-01-29 22:30:19 +01:00 |
|
Dolu1990
|
0997592768
|
fpu mul sems all good excepted subnormal rounding
|
2021-01-29 16:13:49 +01:00 |
|
Dolu1990
|
3c4df1e963
|
fpu moved overflow rounding to writeback
|
2021-01-29 14:37:52 +01:00 |
|
Dolu1990
|
fc3e6a6d0a
|
fpu add rounding is ok excepted infinity result
|
2021-01-28 20:26:43 +01:00 |
|
Dolu1990
|
1ae84ea83b
|
fpu added proper rounding for add (need to manage substraction)
|
2021-01-28 00:25:16 +01:00 |
|
Dolu1990
|
195e4c422d
|
fpu now integrate f2i shifter withing the subnormal shifter
|
2021-01-27 12:11:30 +01:00 |
|
Dolu1990
|
444bcdba0a
|
fpu merged i2f with load pipeline
|
2021-01-26 15:28:09 +01:00 |
|
Dolu1990
|
3334364f5f
|
fpu added more tests for min max sqrt div
|
2021-01-26 12:50:23 +01:00 |
|
Dolu1990
|
f818fb3ba4
|
fpu got proper subnormal support, pass add/mul
|
2021-01-26 10:49:53 +01:00 |
|
Dolu1990
|
d6e8a5ef22
|
VexRiscvSmpLitex options refractoring
|
2021-01-23 20:16:58 +01:00 |
|
Dolu1990
|
ce143e06f2
|
VexRiscvSmpLitex --in-order-decoder --wishbone-memory added
|
2021-01-23 17:48:34 +01:00 |
|
Dolu1990
|
bdb5bc1180
|
fpu div implement some special values handeling
|
2021-01-22 20:47:31 +01:00 |
|
Dolu1990
|
7d79685fe2
|
fpu mul now support special floats values and better rounding
|
2021-01-22 18:15:45 +01:00 |
|
Dolu1990
|
4bd637cf88
|
fpu add now support special floats values and better rounding
|
2021-01-22 14:55:37 +01:00 |
|
Dolu1990
|
bcd140fc42
|
Add vexRiscvConfig.withMmu option
|
2021-01-21 13:28:09 +01:00 |
|
Dolu1990
|
ccd13b7e9e
|
fpu zero/nan wip
|
2021-01-21 12:13:25 +01:00 |
|
Dolu1990
|
50a69d8d4a
|
Merge pull request #163 from lindemer/pmp-warl
Make all PMP registers WARL according to specification
|
2021-01-21 10:50:49 +01:00 |
Samuel Lindemer
|
6c13e6458f
|
Remove registers storing PMP region bounds
|
2021-01-20 14:27:38 +01:00 |
|
Dolu1990
|
ac5844f393
|
fpu add signed i2f/f2i
|
2021-01-20 13:15:29 +01:00 |
|
Dolu1990
|
15d79ef330
|
fpu implement fclass and args for sub, fma, max, fcmp, fsgnj
|
2021-01-20 12:01:08 +01:00 |
|
Samuel Lindemer
|
828ea96006
|
PMP registers are now WARL
|
2021-01-20 09:27:35 +01:00 |
|
Dolu1990
|
11349a71fa
|
fpu FpuPlugin now implement all instructions.
Remains the FPuCore to implement cmd.arg and floating point corner cases
|
2021-01-19 17:57:41 +01:00 |
|
Dolu1990
|
9f18045329
|
fpu add sstatus.fs
|
2021-01-19 16:06:16 +01:00 |
|
Dolu1990
|
a7d148d0ff
|
fpu add vex csr
|
2021-01-19 15:53:11 +01:00 |
|
Dolu1990
|
f826a2ce51
|
fpu completion interface added + refractoring
|
2021-01-19 15:13:13 +01:00 |
|
Dolu1990
|
8c4fae8bf2
|
fpu add min/sgnj/fmv
|
2021-01-19 13:27:42 +01:00 |
|
Dolu1990
|
ed68c8cf04
|
Merge pull request #162 from lindemer/paging
Distinguish between page faults from MMU and access faults from PMP
|
2021-01-18 22:18:06 +01:00 |
|
Dolu1990
|
d7220031d4
|
fpu vex i2f works
|
2021-01-18 17:18:01 +01:00 |
|
Dolu1990
|
d4b877d415
|
fpu vex cmp/fle works
|
2021-01-18 15:09:30 +01:00 |
|
Dolu1990
|
6cb498cdb2
|
fpu merge load/commit
|
2021-01-18 13:09:08 +01:00 |
|
Dolu1990
|
a9d8c0a19f
|
fpu wip
|
2021-01-18 11:38:26 +01:00 |
|
Dolu1990
|
3cda7c1f1b
|
fpu wip
|
2021-01-15 14:03:37 +01:00 |
|
Dolu1990
|
04499c0b76
|
FPU sqrt functional
|
2021-01-14 18:33:24 +01:00 |
|
Dolu1990
|
85dd5dbf8e
|
fpu div functional, sqrt wip
|
2021-01-14 15:56:56 +01:00 |
|
Samuel Lindemer
|
5e6c645461
|
Distinguish between page faults from MMU and access faults from PMP
|
2021-01-14 09:45:38 +01:00 |
|
Dolu1990
|
8761d0d9ee
|
FpuCore can add/mul/fma/store/load
|
2021-01-13 18:28:26 +01:00 |
|
Dolu1990
|
6e0be6e18c
|
Cfu add state index and cfu index
|
2021-01-11 13:44:04 +01:00 |
|
Dolu1990
|
930bdf9dda
|
DataCache increase syncPendingMax to 32 and use a sync queue instead of async one
|
2021-01-04 10:59:21 +01:00 |
|
Dolu1990
|
780ad01ac0
|
Add AES-instruction support
|
2020-12-21 11:52:55 +01:00 |