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VexRiscv
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570 Commits

Author SHA1 Message Date
Tom Verbeure 6038730e53 Merge branch 'master' of https://github.com/SpinalHDL/VexRiscv 2019-03-27 19:49:09 -07:00
Dolu1990 d63c6818df
Merge pull request #67 from tomverbeure/manual 
Some minor updated to the manual
 2019-03-25 02:07:42 +01:00
Tom Verbeure 3d5e941aef Merge branch 'master' of https://github.com/SpinalHDL/VexRiscv 2019-03-24 23:56:23 +00:00
Dolu1990 d70f970b15
Merge pull request #66 from tomverbeure/IBusSimple_to_PipelinedMemoryBus 
Add getPipelinedMemoryBusConfig()
 2019-03-24 08:05:21 +01:00
Tom Verbeure ea62fd0e16 Same thing for DBusSimpleBus. 2019-03-23 23:36:13 +00:00
Tom Verbeure 1afad4f240 Ignore vim backup files. 2019-03-23 22:34:22 +00:00
Tom Verbeure 95c3e436dc Make toPipelinedMemoryBus() just like the other busses 2019-03-23 22:32:48 +00:00
Tom Verbeure 59a2817e5c Update DecoderSimplePlugin manual. 2019-03-21 05:53:27 +00:00
Tom Verbeure 3f5605f22e Fix table. 2019-03-21 05:36:30 +00:00
Tom Verbeure 02a6312912 Update IBusCachedPlugin manual. 2019-03-21 05:34:15 +00:00
Tom Verbeure b7ddd02fc6 IBusSimplePlugin README. 2019-03-21 05:17:07 +00:00
Dolu1990 46f10bacb2
Merge pull request #64 from tomverbeure/MulSimple 
MulSimplePlugin
 2019-03-19 20:39:28 +01:00
Tom Verbeure b63395435f SimpleMul core. 2019-03-16 15:44:18 +00:00
Tom Verbeure 5bc53c08ce Merge branch 'master' of https://github.com/SpinalHDL/VexRiscv into MulSimple 2019-03-16 15:39:07 +00:00
Dolu1990 9a61ff8347 Merge remote-tracking branch 'origin/dev' 2019-03-10 11:14:09 +01:00
Dolu1990 2e0b63bc67 SpinalHDL 1.3.2 2019-03-10 11:12:43 +01:00
Dolu1990 bad60f39cd Fix Decoding benchmark 2019-03-10 11:12:32 +01:00
Dolu1990 434793711b fix part of #59 2019-02-26 17:26:42 +01:00
Dolu1990 b9922105f0 Fix readme demo path 2019-02-26 17:22:13 +01:00
Dolu1990 e0214056ce
Merge pull request #58 from mithro/patch-1 
Fix image in README.
 2019-02-23 09:22:38 +01:00
Tim Ansell 7594cbd902
Fixing images in README in iCE40-hx8k_breakout_board_xip directory too. 2019-02-22 14:57:07 -08:00
Tim Ansell 5c6cc29304
Fixing other image. 2019-02-22 14:55:18 -08:00
Tim Ansell c9f4a09de0
Fix image in README. 2019-02-22 14:52:09 -08:00
Dolu1990 e0c8ac01d2 Add custom external interrupts 2019-02-03 15:20:34 +01:00
Dolu1990 11f55359c6 IBusCache can now avoid injectorStage in singleStage mode 2019-01-30 01:37:47 +01:00
Dolu1990 56e3321394 cpp regresion now print the time of failure 2019-01-30 01:36:24 +01:00
Dolu1990 285f6bb6ac
Update README.md 
Remove JDK constraints
 2019-01-29 12:35:12 +01:00
Dolu1990 f4598fbd0a Add tightly coupled interface to the i$ 2019-01-21 23:46:18 +01:00
Dolu1990 8f1b4cc8e5 Merge branch 'master' into dev 2019-01-16 16:32:12 +01:00
Dolu1990 b5caca54cd restore all feature in TestsWorkspace 2019-01-16 15:25:50 +01:00
Dolu1990 f4f854ae4f SpinalHDL 1.3.1 2019-01-14 13:32:16 +01:00
Dolu1990 dcdfa79024 fix run-main into runMain 2019-01-03 20:07:38 +01:00
Dolu1990 414d2aba54 Merge remote-tracking branch 'origin/dev' 2018-12-30 15:54:14 +01:00
Dolu1990 927ab6d127 Merge remote-tracking branch 'origin/master' into dev 2018-12-30 15:53:25 +01:00
Dolu1990 92065a1a10 Update to SpinalHDL 1.3.0 2018-12-30 15:51:46 +01:00
Dolu1990 dd42e30c61 Merge remote-tracking branch 'origin/master' into dev 2018-12-29 14:04:07 +01:00
Dolu1990 d617bafb08 Roll back VexRiscvAvalonForSim to use caches 2018-12-25 00:15:23 +01:00
Dolu1990 1da055dc34
Merge pull request #49 from cutephoton/avalon 
Avalon: Debug Clock Domain for JTAG
 2018-12-23 16:27:50 +01:00
Brett Foster 961abb3cf1 Avalon: Debug Clock Domain for JTAG 
This change ensures that the clock domain for the JTAG interface
uses the debug plugin's domain. Otherwise, resetting the processor
will put the jtag debugger in to reset as well.

See SpinalHDL/VexRiscv#48
 2018-12-22 07:58:59 -08:00
Dolu1990 76ebfb2243 Fix machine mode to supervisor delegation 2018-12-10 13:15:03 +01:00
Dolu1990 d9029c2efc Fix #46 by filling missing return statements 2018-12-10 01:44:47 +01:00
Dolu1990 281d61bbe1 regression fix hex << dec #46 2018-12-09 16:37:16 +01:00
Dolu1990 1fbb81a4d9 regression fix delete [] #46 2018-12-09 15:40:02 +01:00
Dolu1990 cf80c63c22 fix travis 2018-12-08 15:16:17 +01:00
Dolu1990 f121ce1ed5 add sanity asserts in regression #46 2018-12-08 14:10:18 +01:00
Dolu1990 9330945623 fix regression makefile 2018-12-07 23:50:13 +01:00
Dolu1990 52419fd7ad Regression remove dplus stuff #46 2018-12-07 23:47:49 +01:00
Dolu1990 68fdbe60cc verilator regression fix missing fclose #46 2018-12-07 23:43:19 +01:00
Dolu1990 6334f430fe
Update README.md 
Fix #44
 2018-12-04 19:07:51 +01:00
Dolu1990 eca54585b0 Fix hardware breakpoint 2018-12-04 16:57:24 +01:00