Charles Papon
|
11a63491bd
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Add YAML feature to store CPU info
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2017-06-09 16:06:18 +02:00 |
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Charles Papon
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4b9668c063
|
Remove speed factor overriding when Trace
|
2017-06-09 08:41:12 +02:00 |
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Charles Papon
|
f46ec583d6
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Briey is now working with DataCache on FPGA
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2017-06-07 23:02:34 +02:00 |
|
Dolu1990
|
8dcf5cf68a
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Add missing import in Briey testbench
|
2017-06-07 16:56:29 +02:00 |
|
Charles Papon
|
8da413dec3
|
Briey SoC is now working with openOCD TCP JTAG connection. (GDB OK)
Add SDRAM Verilator model
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2017-06-07 04:19:35 +02:00 |
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Charles Papon
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1e18daecc0
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Add ICache and DCache axi bridges functions
Add StaticMemoryTranslationPlugin
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2017-06-01 17:54:56 +02:00 |
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Charles Papon
|
ac16558b6b
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Add haltItByOther
Axi4, remove some pipelining
|
2017-05-30 17:49:29 +02:00 |
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Charles Papon
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6b62d8da52
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VexRiscv in Briey SoC is working on FPGA (including jtag debugging)
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2017-05-29 21:17:14 +02:00 |
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Charles Papon
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213e154b40
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Fix regression test debugPlugin bus
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2017-05-28 17:41:09 +02:00 |
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Charles Papon
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8dddc7e334
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GDB + openOCD successfully connect !
|
2017-05-25 13:36:54 +02:00 |
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Charles Papon
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75f6b78daf
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OpenOCD successfuly connected to target
|
2017-05-24 23:53:31 +02:00 |
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Charles Papon
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1efed60307
|
Fix DebugPlugin
Add DebugPlugin regression (PASS)
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2017-05-22 19:23:11 +02:00 |
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Charles Papon
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cc875d1c0b
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Add TCP server socket to manage debug access from openOCD (as instance)
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2017-05-22 00:42:19 +02:00 |
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Charles Papon
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5cda2632df
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Start implementing debugPlugin test infrastructures
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2017-05-21 23:50:40 +02:00 |
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Charles Papon
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9995c5109d
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move tests
|
2017-05-21 16:53:48 +02:00 |
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Charles Papon
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6c1d953647
|
DebugPlugin fully implemented
|
2017-05-20 18:15:15 +02:00 |
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Charles Papon
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619739d33a
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preliminary DebugPlugin
|
2017-05-20 15:16:45 +02:00 |
|
Dolu1990
|
cabf602efc
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Update README.md
|
2017-05-19 17:13:33 +02:00 |
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Charles Papon
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a5364ad001
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Add flush support instruction into the instruction cache
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2017-05-19 11:20:33 +02:00 |
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Charles Papon
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736478ff1d
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CsrPlugin now catch illegal CSR access (wrong address + to low privilege level)
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2017-05-09 00:40:44 +02:00 |
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Charles Papon
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fe184636dd
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Improve CsrPlugin FMax
|
2017-05-08 22:59:05 +02:00 |
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Charles Papon
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c69fdf7987
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Add basics of the USER mode to CsrPlugin
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2017-05-07 23:41:54 +02:00 |
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Charles Papon
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579e93bb5a
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Rename MachineCsr plugin into CsrPlugin
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2017-05-07 22:26:17 +02:00 |
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Charles Papon
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392f3a7d8c
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Add PrivilegeService (User) (not implemented)
Split caches from their plugins file
|
2017-05-07 20:16:41 +02:00 |
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Charles Papon
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a51c27970b
|
Add opcode for clean/invalidate the datacache
Change mmu opcodes
|
2017-05-07 16:02:55 +02:00 |
|
Charles Papon
|
4d6a6fbb02
|
Fix Instruction Data cache exceptions
Pass all tests including CSR/FreeRTOS
|
2017-05-07 12:51:47 +02:00 |
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Charles Papon
|
ca1bc9cf69
|
DataCache plugin now support all exceptions
|
2017-05-07 10:44:41 +02:00 |
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Charles Papon
|
5ba8ab7947
|
DataCache add invalidate/clean/invalidateClean on a virtual address/way
|
2017-05-05 00:43:41 +02:00 |
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Charles Papon
|
48a5dc8e79
|
DCache move the exception bus outside the cache component
|
2017-05-04 21:01:08 +02:00 |
|
Charles Papon
|
534a4c3494
|
mmu working for instruction and data bus (both tested)
|
2017-05-03 18:42:54 +02:00 |
|
Charles Papon
|
c647ef8bb6
|
Rework constructors
|
2017-05-01 20:20:21 +02:00 |
|
Charles Papon
|
889a040f90
|
Fix multi port MMU design
Change machineCSR to handle exceptions from the writeBack stage
Change the DBusCachedPlugin to emit miss exception
|
2017-05-01 14:29:37 +02:00 |
|
Charles Papon
|
2ed33106d6
|
MMU pass simple regression !
|
2017-04-29 19:58:17 +02:00 |
|
Charles Papon
|
227772f19c
|
Add miss files
|
2017-04-28 16:41:44 +02:00 |
|
Charles Papon
|
010ba568f0
|
MMU implemented
Datacached using MMU implemented
It compile, but nothing is tested
|
2017-04-28 16:41:23 +02:00 |
|
Charles Papon
|
ba2ca77114
|
Two stage datacache now pass dhrystone benchmark without error
|
2017-04-23 23:15:38 +02:00 |
|
Charles Papon
|
9040326273
|
WIP two stage DCache, nearly passed the dhrystone benchmark
|
2017-04-23 18:31:16 +02:00 |
|
Charles Papon
|
e00bf028cb
|
Add HazardPessimisticPlugin for light and very good FMAX hazard tracking
|
2017-04-17 17:56:47 +02:00 |
|
Charles Papon
|
024e14ae58
|
Smaller and faster single stage instruction cache
Add fast two stage instruction cache
Remove useless address == 0 checks in the HazardPlugin
|
2017-04-13 18:27:03 +02:00 |
|
Charles Papon
|
c83a157c64
|
IBusCachedPlugin with twoStage config is now compatible with syncronous regfile
|
2017-04-09 11:59:09 +02:00 |
|
Charles Papon
|
9a4c35d7b6
|
IBusCachedPlugin twoStage config fix
|
2017-04-08 18:34:44 +02:00 |
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Charles Papon
|
e3b9e671ec
|
IBusCachedPlugin add two stage cache option for better FMax and better scaling
|
2017-04-08 17:42:13 +02:00 |
|
Charles Papon
|
5c594d6d2a
|
IBusCachedPlugin move memory access outside the pipeline
|
2017-04-07 13:27:47 +02:00 |
|
Charles Papon
|
8f09867bda
|
Cleaning
|
2017-04-07 13:09:31 +02:00 |
|
Charles Papon
|
efb27390a7
|
Better IntAluPlugin
Better SrcPlugin
Better DBusCachedPlugin
|
2017-04-06 01:28:52 +02:00 |
|
Charles Papon
|
2e02a6f0e7
|
DBusCachedPlugin better write to read hazard logic (FMAX)
Add some TODO FMAX comments
|
2017-04-05 18:37:02 +02:00 |
|
Charles Papon
|
179e7f7b4c
|
IBusCachedPlugin add asyncTagMemory option
|
2017-04-05 14:25:11 +02:00 |
|
Charles Papon
|
2b24cbc8e1
|
Add pessimistic harzard options
Add separated add/sum option in srcPlugin
|
2017-04-04 00:25:39 +02:00 |
|
Charles Papon
|
acb85a1fb8
|
Add some decoder comments
|
2017-04-03 01:33:54 +02:00 |
|
Charles Papon
|
8ff05bd2a8
|
Much better decoder using Quine-Mc Cluskey
|
2017-04-02 21:05:25 +02:00 |