Dolu1990
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0668046407
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More smp cluster profiling
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2020-06-05 10:40:51 +02:00 |
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Dolu1990
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97c2dc270c
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Fix typo
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2020-06-04 10:11:30 +02:00 |
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Dolu1990
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89c13bedbd
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Fix litex smp cluster sim
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2020-06-03 16:31:54 +02:00 |
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Dolu1990
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73f88e47cb
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Fix BmbToLitexDram coherency
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2020-06-03 16:31:54 +02:00 |
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Dolu1990
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db50f04653
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Add litexMpCluster
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2020-06-03 16:31:54 +02:00 |
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Dolu1990
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08189ee907
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DebugPlugin now support Bmb
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2020-06-02 19:13:55 +02:00 |
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Dolu1990
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2942d0652a
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fix Briey verilator
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2020-06-01 11:18:25 +02:00 |
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Dolu1990
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5e5c730959
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Add LitexSmpDevCluster with per cpu dedicated litedram ports
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2020-05-29 10:56:55 +02:00 |
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Dolu1990
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bc4a2c3747
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Fix SmpCluster jtag
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2020-05-27 14:19:37 +02:00 |
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Dolu1990
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18cce053a3
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Improve SingleInstructionLimiterPlugin to also include fetch stages
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2020-05-27 14:19:17 +02:00 |
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Dolu1990
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a64fd9cf3b
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Add CsrPlugin external hartid
d$ rsp/sync now decrement pendings by signal amount
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2020-05-20 13:49:10 +02:00 |
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Dolu1990
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380afa3130
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SpinalHDL 1.4.2
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2020-05-20 13:45:52 +02:00 |
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Dolu1990
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c3540bc6e0
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SpinalHDL 1.4.2
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2020-05-20 10:37:52 +02:00 |
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Dolu1990
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24b676ce30
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Merge pull request #124 from tomverbeure/uinstret
Add uinstret support.
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2020-05-20 10:35:42 +02:00 |
Tom Verbeure
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b901651ab5
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Add default value of NONE to uinstret CSR.
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2020-05-19 14:48:35 -07:00 |
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Tom Verbeure
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c74b03b4de
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Add uinstret support.
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2020-05-19 13:40:46 -07:00 |
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Dolu1990
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cf60989ae1
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Litex smp cluster now blackboxify d$ data ram
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2020-05-14 00:05:54 +02:00 |
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Dolu1990
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42fef8bbcd
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Smp cluster now use i$ reduceBankWidth
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2020-05-12 23:59:38 +02:00 |
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Dolu1990
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685c914227
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Add i$ reduceBankWidth to take advantage of multi way by remaping the data location to reduce on chip ram data width
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2020-05-12 23:59:38 +02:00 |
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Dolu1990
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0471c7ad76
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Fix machineCsr test
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2020-05-12 23:55:47 +02:00 |
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Dolu1990
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cb44a474fc
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more smp cluster profiling
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2020-05-12 13:25:55 +02:00 |
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Dolu1990
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63511b19a2
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smp cluster add more profiling
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2020-05-11 10:35:24 +02:00 |
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Charles Papon
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b592b0bff8
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Add regression TRACE_SPORADIC, LINUX_SOC_SMP
regression golden model now properly sync dut exceptions
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2020-05-09 17:00:13 +02:00 |
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Dolu1990
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0a159f06b2
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update smp config
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2020-05-07 22:50:36 +02:00 |
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Dolu1990
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0e76cf9ac8
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i$ now support multi cycle MMU
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2020-05-07 22:50:25 +02:00 |
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Dolu1990
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41ee8fd226
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MmuPlugin now support multiple stages, D$ can now take advantage of that
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2020-05-07 13:37:53 +02:00 |
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Dolu1990
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8e025aeeaa
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more litex smp cluster pipelining
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2020-05-07 13:18:11 +02:00 |
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Dolu1990
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fc0f3a2020
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cleanup mmu interface
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2020-05-06 18:05:20 +02:00 |
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Dolu1990
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6323caf265
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MMU now allow $ to match tag against tlb pyhsical values directly
D$ retiming
D$ directTlbHit feature added for better timings
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2020-05-06 17:09:46 +02:00 |
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Dolu1990
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ed4a89e4af
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more pipelineing in Litex SMP cluster interconnect
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2020-05-06 17:06:45 +02:00 |
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Dolu1990
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8043feebd5
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More VexRiscv smp cluster probes
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2020-05-06 17:06:17 +02:00 |
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Dolu1990
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09724e907b
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play around with CSR synthesis impact on design size
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2020-05-05 00:32:59 +02:00 |
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Dolu1990
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c16f2ed787
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Add probes in SmpCluster sim
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2020-05-04 12:54:28 +02:00 |
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Dolu1990
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b0f7f37ac8
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D$ now support memDataWidth > 32
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2020-05-04 12:54:16 +02:00 |
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Dolu1990
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93b386e16e
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litex smp cluster now use OO decoder
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2020-05-02 23:44:58 +02:00 |
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Dolu1990
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f0745eb0d9
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update SMP line size to 64 bytes
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2020-05-02 23:44:27 +02:00 |
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Dolu1990
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09ac23b78f
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Fix SMP fence lock when 4 stages CPU
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2020-05-01 12:45:16 +02:00 |
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Dolu1990
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f5f30615ba
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Got litex SMP cluster to work on FPGA
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2020-05-01 11:14:52 +02:00 |
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Dolu1990
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dc0da9662a
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Update SMP fence (final)
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2020-05-01 11:14:11 +02:00 |
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Dolu1990
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7c50fa6d55
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SmpCluster now use i$ line of 64 bytes
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2020-04-29 14:03:00 +02:00 |
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Dolu1990
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9e9d28bfa6
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d$ now implement consistancy hazard by using writeback redo
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2020-04-29 14:02:41 +02:00 |
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Dolu1990
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86e0cbc1f3
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I$ with memDataWidth > cpuDataWidth now mux memWords into cpuWords before the decode stage by default. Add twoCycleRamInnerMux option to move that to the decode stage
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2020-04-29 13:59:43 +02:00 |
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Dolu1990
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7b80e1fc30
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Set SMP workspace to use i$ memDataWidth of 128 bits
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2020-04-28 22:11:41 +02:00 |
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Dolu1990
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eee9927baf
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IBusCachedPlugin now support memory data width multiple of 32
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2020-04-28 22:10:56 +02:00 |
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Dolu1990
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23b8c40cab
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update travis verilator
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2020-04-28 16:19:00 +02:00 |
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Dolu1990
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03a0445775
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Fix SMP for configuration without writeback stage.
Include SMP core into the single core tests regressions
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2020-04-28 15:50:20 +02:00 |
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Dolu1990
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4a49b23636
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Fix regression
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2020-04-28 14:38:27 +02:00 |
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Dolu1990
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3ba509931c
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Add VexRiscvSmpLitexCluster with the required pipelining to get proper FMax
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2020-04-27 17:38:06 +02:00 |
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Dolu1990
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5fd0b220cd
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CsrPlugin add openSbi config
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2020-04-27 17:37:30 +02:00 |
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Dolu1990
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0c59dd9ed3
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SMP fence now ensure ordering for all kinds of memory transfers
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2020-04-27 17:37:15 +02:00 |