6aa6191240
Merge branch 'master' into dev
...
# Conflicts:
# build.sbt
# src/main/scala/vexriscv/Riscv.scala
# src/main/scala/vexriscv/ip/DataCache.scala
# src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
# src/main/scala/vexriscv/plugin/MmuPlugin.scala
# src/test/cpp/regression/makefile
# src/test/scala/vexriscv/TestIndividualFeatures.scala
2021-01-30 20:30:21 +01:00
d6e8a5ef22
VexRiscvSmpLitex options refractoring
2021-01-23 20:16:58 +01:00
ce143e06f2
VexRiscvSmpLitex --in-order-decoder --wishbone-memory added
2021-01-23 17:48:34 +01:00
bcd140fc42
Add vexRiscvConfig.withMmu option
2021-01-21 13:28:09 +01:00
50a69d8d4a
Merge pull request #163 from lindemer/pmp-warl
...
Make all PMP registers WARL according to specification
2021-01-21 10:50:49 +01:00
6c13e6458f
Remove registers storing PMP region bounds
2021-01-20 14:27:38 +01:00
828ea96006
PMP registers are now WARL
2021-01-20 09:27:35 +01:00
ed68c8cf04
Merge pull request #162 from lindemer/paging
...
Distinguish between page faults from MMU and access faults from PMP
2021-01-18 22:18:06 +01:00
04499c0b76
FPU sqrt functional
2021-01-14 18:33:24 +01:00
85dd5dbf8e
fpu div functional, sqrt wip
2021-01-14 15:56:56 +01:00
5e6c645461
Distinguish between page faults from MMU and access faults from PMP
2021-01-14 09:45:38 +01:00
8761d0d9ee
FpuCore can add/mul/fma/store/load
2021-01-13 18:28:26 +01:00
6e0be6e18c
Cfu add state index and cfu index
2021-01-11 13:44:04 +01:00
930bdf9dda
DataCache increase syncPendingMax to 32 and use a sync queue instead of async one
2021-01-04 10:59:21 +01:00
780ad01ac0
Add AES-instruction support
2020-12-21 11:52:55 +01:00
d2855fcfca
Merge pull request #147 from lindemer/pmp
...
Physical Memory Protection (PMP) plugin
2020-12-11 15:22:28 +01:00
c59499ec03
typo
2020-12-11 14:13:33 +01:00
eaff52b264
Add comments to the AesPlugin
2020-12-11 13:51:10 +01:00
6da09967f8
Add comments to the AesPlugin
2020-12-11 13:46:55 +01:00
7d699dcc13
Remove PMP from MachineOs test defaults
2020-12-10 09:42:27 +01:00
f2ce2eab00
PMP plugin passes regression tests
2020-12-07 12:04:45 +01:00
763eebeeba
Add TOR support, tests pass on GenZephyr
2020-12-04 17:13:31 +01:00
5cb5061d9b
PMP passes test with GenZephyr, but pipeline flushes have been disabled
2020-12-03 17:29:31 +01:00
9a6931a54c
CfuPlugin improve writeback buffering
2020-12-03 16:21:52 +01:00
987de8fb6a
Lock PMP address registers in golden model
2020-12-02 14:18:17 +01:00
14c39a0070
Merge remote-tracking branch 'upstream/master' into pmp
2020-12-02 14:08:32 +01:00
872aa19d83
Add PMP to golden model
2020-12-02 12:27:26 +01:00
d5b1a8f565
Add PMP test to regression suite
2020-12-01 18:38:06 +01:00
45ff78d068
VexRiscvSmpClusterGen.dBusCmdMasterPipe option added
2020-12-01 13:51:10 +01:00
c5023ad973
Add PMP regression test
2020-12-01 09:10:24 +01:00
1b65a9e523
remove libts-dev from readme
2020-11-30 16:11:00 +01:00
2d0ebf1ef5
Flush pipeline after PMP CSR writes
2020-11-25 15:38:34 +01:00
e0ae46e794
Fix Csr ReadWrite interration with DBusCachedPlugin execute halt
...
# Conflicts:
# src/main/scala/vexriscv/plugin/CsrPlugin.scala
2020-11-18 14:43:24 +01:00
832218dbec
DBusCachedPlugin increase pendingMax to 64 to hide memory latency when saving a full context
2020-11-16 12:38:29 +01:00
ba523c627a
Fix Csr ReadWrite interration with DBusCachedPlugin execute halt
2020-11-16 12:37:48 +01:00
dae633aa7d
Merge pull request #150 from banahogg/patch-1
...
Update GCC prebuild instructions for sifive.com reorg
2020-11-15 11:25:50 +01:00
d1691e9478
Update GCC prebuild instructions for sifive.com reorg
2020-11-14 17:31:50 -08:00
c1b0869c21
AesPlugin is now little endian
2020-11-12 15:07:27 +01:00
1b2a2ebaca
DBusCachedPlugin miss decoded aquire fix
2020-11-12 15:07:07 +01:00
05e725174c
AesPlugin added, work with dropbear encryption, seem ok for decryption (barmetal)
2020-11-02 17:14:52 +01:00
9abe19317d
RegFilePlugin.x0Init do less assumption on other plugin behaviour
2020-11-02 17:01:17 +01:00
97fe279f7b
Enable PMP register lock
2020-10-29 13:37:21 +01:00
dc9246715d
Do not allow jtag ebreak outside machine mode
2020-10-28 13:00:16 +01:00
4209dc2792
Fix CsrPlugin privilege crossing
2020-10-28 13:00:15 +01:00
576e21d75d
Do not allow jtag ebreak outside machine mode
2020-10-28 12:58:24 +01:00
abebeaea1f
Fix CsrPlugin privilege crossing
2020-10-28 12:57:20 +01:00
fc2c8a7c37
Initial commit of PMP plugin
2020-10-27 09:38:58 +01:00
fe342c347c
CfuBusParameter has now a few default values
2020-10-23 11:06:24 +02:00
d490f903ea
Merge pull request #145 from zeldin/bigendian2
...
Update big endian instruction encoding
2020-10-21 12:56:56 +02:00
6c8e97f825
Update big endian instruction encoding
...
Between draft-20181101-ebe1ca4 and draft-20190622-6993896 of the
RISC-V Instruction Set Manual, the wording was changed from requiring
"natural endianness" of instruction parcels to require them to be
little endian.
Update the big endian instruction pipe to reflect the newer requirement.
2020-10-20 18:05:31 +02:00
Dolu1990
Samuel Lindemer
banahogg
Marcus Comstedt