Dolu1990
|
9462496386
|
Add rvc support and fix rvc with FPU
|
2021-03-25 14:14:19 +01:00 |
|
Dolu1990
|
6f481f51ef
|
Fetcher.decompressor ensure that the decoded instruction do not mutate when the pipeline is stalled (fix FPU cmd fork for rvc without injector stage)
|
2021-03-25 14:13:12 +01:00 |
|
Dolu1990
|
21c91c6b70
|
fpu now lift wfi
|
2021-03-24 16:21:37 +01:00 |
|
Dolu1990
|
925edd160e
|
RVC implement RVF RVD
Rework RVC_GEN
|
2021-03-24 12:04:27 +01:00 |
|
Dolu1990
|
704423f27f
|
Merge pull request #167 from rdolbeau/support_FDwC
Attempt at supporting C (ompressed) and F/D (floating-point) together
|
2021-03-24 11:59:05 +01:00 |
Romain Dolbeau
|
8495fe3dde
|
Attempt at supporting C (ompressed) and F/D (floating-point) together
|
2021-03-24 11:07:09 +01:00 |
|
Dolu1990
|
da458dea7e
|
litex cluster add cpuPerFpu option
|
2021-03-23 20:00:50 +01:00 |
|
Dolu1990
|
80f64f0f9f
|
litex better pipelining for better fmax, create one FPU for each 4 cores
|
2021-03-18 11:10:22 +01:00 |
|
Dolu1990
|
6956db2b21
|
fpu add schedulerM2sPipe optino
|
2021-03-18 11:10:22 +01:00 |
|
Dolu1990
|
099dea743b
|
fpu cleanup
|
2021-03-18 10:54:51 +01:00 |
|
Dolu1990
|
f6e620196d
|
litex add fpu suport
|
2021-03-17 13:19:41 +01:00 |
|
Dolu1990
|
1a0aa37d6f
|
Merge branch 'fiber' into dev
|
2021-03-17 10:02:09 +01:00 |
|
Dolu1990
|
530554d19c
|
fix fpu diagram
|
2021-03-16 14:52:57 +01:00 |
|
Dolu1990
|
e23687c45d
|
Handle ClockDomain improvements
|
2021-03-16 14:46:30 +01:00 |
|
Dolu1990
|
02c572b6f1
|
fpu improve FMax and add asyncronus regfile support
|
2021-03-16 14:45:59 +01:00 |
|
Dolu1990
|
0d628b4706
|
fpu add doc
|
2021-03-16 14:44:31 +01:00 |
|
Dolu1990
|
5aa1f2e996
|
fpu improve pipline cycles
|
2021-03-15 17:27:14 +01:00 |
|
Dolu1990
|
341c159d06
|
data cache relax assert into error
|
2021-03-15 14:43:22 +01:00 |
|
Dolu1990
|
3a34b8dae2
|
Merge branch 'dev' into fiber
# Conflicts:
# src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
# src/main/scala/vexriscv/plugin/MulPlugin.scala
|
2021-03-15 10:35:02 +01:00 |
|
Charles Papon
|
ff4e5e4666
|
wipe generator
|
2021-03-11 18:02:02 +01:00 |
|
Charles Papon
|
adc37b269c
|
FpuPlugin.pending is now 6 bits
|
2021-03-11 13:06:50 +01:00 |
|
Charles Papon
|
845cfcb966
|
DebugPlugin.fromBscane2 added
|
2021-03-10 20:35:44 +01:00 |
|
Charles Papon
|
67d2f72a4b
|
fiber sync
|
2021-03-07 20:43:02 +01:00 |
|
Dolu1990
|
e384bfe145
|
fiber update
|
2021-03-05 22:04:20 +01:00 |
|
Dolu1990
|
fd234bbf9e
|
fix cfu gen error
|
2021-03-05 09:41:05 +01:00 |
|
Dolu1990
|
aee8841438
|
CFU ensure that CFU_IN_FLIGHT do not produce false positive when the pipeline is stuck
|
2021-03-05 09:41:05 +01:00 |
|
Dolu1990
|
0530d22a1d
|
sync
|
2021-03-04 16:06:18 +01:00 |
|
Dolu1990
|
caf1bde49b
|
Add MuraxAsicBlackBox example
|
2021-03-04 10:16:45 +01:00 |
|
Dolu1990
|
4bdab667cc
|
fpu fix cmd / commit race condition
|
2021-03-02 19:39:55 +01:00 |
|
Dolu1990
|
636d53cf63
|
fpu now track commits using a counter per pipeline per port
|
2021-03-02 16:13:12 +01:00 |
|
Dolu1990
|
81c193af1f
|
Improve subnormal/normal rounding
|
2021-02-26 16:32:42 +01:00 |
|
Dolu1990
|
de81da36eb
|
Fpu fix a few div special cases
|
2021-02-25 19:39:57 +01:00 |
|
Dolu1990
|
de09ed3fcb
|
fpu added exact div/sqrt implementations using iterative approaches
|
2021-02-25 15:28:38 +01:00 |
|
Dolu1990
|
be81cc1e0e
|
CfuPlugin.response_ok removed
|
2021-02-23 12:23:48 +01:00 |
|
Dolu1990
|
47673863fb
|
fpu test cleaning
|
2021-02-22 19:27:55 +01:00 |
|
Dolu1990
|
b1f4c06d4e
|
fpu fix arbitration/lock bugs
add getVexRiscvRegressionArgs
|
2021-02-22 19:27:26 +01:00 |
|
Dolu1990
|
a6e89fe05c
|
fpu vex regression goldenModel can now assert FPU interface
|
2021-02-19 17:55:56 +01:00 |
|
Dolu1990
|
3f226b758c
|
fpu fix exception flag handeling
|
2021-02-19 13:03:48 +01:00 |
|
Dolu1990
|
e504afbf18
|
fpu integration wip, got mandelbrot to work in linux with no inline (crash when inlined)
|
2021-02-19 11:26:28 +01:00 |
|
Dolu1990
|
8537d18b16
|
fpu improve fmax
|
2021-02-17 16:35:52 +01:00 |
|
Dolu1990
|
1e647f799c
|
fpu Fix VexRiscv integration and add software f64 tests (pass)
|
2021-02-17 12:33:27 +01:00 |
|
Dolu1990
|
06b7a91de4
|
MulPlugin fix buffer interraction with partial regfile bypass
|
2021-02-17 11:35:17 +01:00 |
|
Dolu1990
|
f180ba2fc9
|
fpu double fixes
DataCache now support wide load/store
|
2021-02-16 15:38:51 +01:00 |
|
Dolu1990
|
8b2a2afb6f
|
VexRIscvSmpCluster add options
|
2021-02-16 14:42:31 +01:00 |
|
Dolu1990
|
1752b9e6d6
|
DataCache.toBmb with aggregation sync path pipelined
|
2021-02-16 14:17:21 +01:00 |
|
Dolu1990
|
fe690528f7
|
MulPlugin.outputBuffer feature added
|
2021-02-16 14:16:57 +01:00 |
|
Dolu1990
|
3b99090879
|
VexRiscvConfig.get added
|
2021-02-16 14:15:20 +01:00 |
|
Dolu1990
|
7d3b35c32c
|
fpu f64/f32 pass all tests
|
2021-02-12 14:48:44 +01:00 |
|
Dolu1990
|
9a25a12879
|
fpu add FCVT_X_X
|
2021-02-11 17:40:35 +01:00 |
|
Dolu1990
|
82dfd10dba
|
fpu fix f32 tests for f64 fpu
|
2021-02-11 16:42:17 +01:00 |