Hardware/VexRiscv
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579 commits 39 branches 2 tags 15 MiB
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380 commits

Author SHA1 Message Date
Dolu1990
9d55283b3b Machine mode emulator 2019-03-25 02:00:19 +01:00
Dolu1990
6c0608f0dd #60 
Add LitexSoC workspace / linux loading.
Need to emulate peripherals and adapte the kernel now.
Probably also need some machine mode emulation
Software time !
 2019-03-24 10:52:56 +01:00
Dolu1990
0656a49332 Make xtval more compliant 2019-03-23 20:12:36 +01:00
Dolu1990
7159237104 Fix csrrs/csrrc for xip registers 2019-03-23 18:11:26 +01:00
Dolu1990
505bff6f45 CSR Plugin now implement interruptions as specified in the spec 2019-03-23 12:56:04 +01:00
Dolu1990
3652ede130 Add mdeleg tests 2019-03-23 11:41:10 +01:00
Dolu1990
f7b793b7bf Add SSTATUS.SUM/MXR feature, need testing 2019-03-22 15:49:36 +01:00
Dolu1990
e4cdc2397a MMU pass all test, need to and SUM and MXR and it's all ok 2019-03-22 14:52:49 +01:00
Dolu1990
2b458fc642 Added MMU superpage support, pass MMU tests 2019-03-22 12:23:47 +01:00
Dolu1990
af2acbd46e Got the new MMU design to pass simple tests #60 2019-03-22 01:10:17 +01:00
Dolu1990
7cbe399f1f Fix some supervisor CSR access 2019-03-20 23:25:52 +01:00
Dolu1990
39b2803914 Fix some CsrPlugin flags issues 2019-03-20 20:27:47 +01:00
Dolu1990
6c2fe934fd Bring changes and fixies from @kgugala @daveshah1. Thanks guys ! 2019-03-20 16:27:35 +01:00
Dolu1990
130a69eeae Pass regressions machinemode with CSR config including Supervisor 2019-03-20 14:14:59 +01:00
Dolu1990
d205f88fb8 riscv golden model and RTL pass all current regressions 
add RVC into the linux config
 2019-03-20 12:17:43 +01:00
Dolu1990
ccc3b63d7c Enable golden model check for all regressions 
Need to implement missing CSR of the golden model
 2019-03-20 01:12:03 +01:00
Dolu1990
8f22365959 Disable MMU in machine mode 2019-03-19 22:21:30 +01:00
Dolu1990
3fbc2f4458 Fix generation 2019-03-19 20:29:28 +01:00
Dolu1990
915db9d6c9 cleaning 2019-03-18 20:50:19 +01:00
Dolu1990
001ca45c57 Add cachless dBus IBus access right checks 2019-03-18 12:52:22 +01:00
Dolu1990
c490838202 Added MMU support into cacheless DBus IBus plugins (for testing purposes) 
Probably full of bugs, need testing
 2019-03-18 12:17:43 +01:00
Dolu1990
ffa489d211 hardware refilled MmuPlugin wip 2019-03-17 21:06:47 +01:00
Dolu1990
bad60f39cd Fix Decoding benchmark 2019-03-10 11:12:32 +01:00
Dolu1990
434793711b fix part of #59 2019-02-26 17:26:42 +01:00
Dolu1990
e0c8ac01d2 Add custom external interrupts 2019-02-03 15:20:34 +01:00
Dolu1990
11f55359c6 IBusCache can now avoid injectorStage in singleStage mode 2019-01-30 01:37:47 +01:00
Dolu1990
f4598fbd0a Add tightly coupled interface to the i$ 2019-01-21 23:46:18 +01:00
Dolu1990
b5caca54cd restore all feature in TestsWorkspace 2019-01-16 15:25:50 +01:00
Dolu1990
927ab6d127 Merge remote-tracking branch 'origin/master' into dev 2018-12-30 15:53:25 +01:00
Dolu1990
dd42e30c61 Merge remote-tracking branch 'origin/master' into dev 2018-12-29 14:04:07 +01:00
Dolu1990
d617bafb08 Roll back VexRiscvAvalonForSim to use caches 2018-12-25 00:15:23 +01:00
Brett Foster
961abb3cf1 Avalon: Debug Clock Domain for JTAG 
This change ensures that the clock domain for the JTAG interface
uses the debug plugin's domain. Otherwise, resetting the processor
will put the jtag debugger in to reset as well.

See SpinalHDL/VexRiscv#48
 2018-12-22 07:58:59 -08:00
Dolu1990
76ebfb2243 Fix machine mode to supervisor delegation 2018-12-10 13:15:03 +01:00
Dolu1990
eca54585b0 Fix hardware breakpoint 2018-12-04 16:57:24 +01:00
Dolu1990
ac1ed40b80 Move things into SpinalHDL lib 2018-12-01 18:25:18 +01:00
Dolu1990
3d71045159 DebugPlugin doesn't require memory/writeback stage anymore 2018-12-01 18:24:33 +01:00
Dolu1990
58d7a4784d move HexTools into SpinalHDL lib 2018-11-30 17:39:33 +01:00
Dolu1990
b1b7da4f10 Rename SimpleBus into PipelinedMemoryBus 
Move PipelinedMemoryBus into SpinalHDL lib
 2018-11-30 17:37:17 +01:00
Dolu1990
2f6a2dfccc Add configs setup in SimpleBusInterconnect 2018-11-29 16:14:45 +01:00
Dolu1990
7075e08d9f Hazarplugin tell to branch plugin if the RS are hazardous in the execute stage 2018-11-24 13:38:54 +01:00
Dolu1990
c2b9544794 Allow iBusCached plugin to be used when no memory stage is present 2018-11-24 13:37:53 +01:00
Dolu1990
0086de9e36 Fix CsrPlugin catch illegalAccess 
Add dhrystone optimized divider
cleaning
 2018-11-20 19:39:17 +01:00
Dolu1990
75d4d049d7 Add shadow regfile 
various cleaning
 2018-11-16 17:06:11 +01:00
Dolu1990
cc48fc7403 add fenceiGenAsANop 2018-11-13 15:17:35 +01:00
Dolu1990
0d92a5e5cd Add many little options to reduce area 2018-11-12 14:14:34 +01:00
Dolu1990
fb9ea11a5e Allow VexRiscv to suppress the memory and the writeback stage, allowing to go downto a 2 stage CPU (FETCH_DECODE, EXECUTE) 2018-11-09 05:41:43 +01:00
Dolu1990
b12e15b112 branch/csr/muldiv minor improvments 2018-11-07 19:27:49 +01:00
Dolu1990
b7f3ee5e06 Fix CsrPlugin pipelined option 2018-11-05 16:22:41 +01:00
Dolu1990
662d76e3aa csrPlugin : avoid using ALU to get SRC1 (which was useless) 2018-11-03 11:29:30 +01:00
Dolu1990
978232fd63 Optimise div iterative plugin done signal 2018-11-03 11:12:37 +01:00