Tom Verbeure
|
1afad4f240
|
Ignore vim backup files.
|
2019-03-23 22:34:22 +00:00 |
|
Tom Verbeure
|
95c3e436dc
|
Make toPipelinedMemoryBus() just like the other busses
|
2019-03-23 22:32:48 +00:00 |
Dolu1990
|
0656a49332
|
Make xtval more compliant
|
2019-03-23 20:12:36 +01:00 |
|
Dolu1990
|
7159237104
|
Fix csrrs/csrrc for xip registers
|
2019-03-23 18:11:26 +01:00 |
|
Dolu1990
|
505bff6f45
|
CSR Plugin now implement interruptions as specified in the spec
|
2019-03-23 12:56:04 +01:00 |
|
Dolu1990
|
3652ede130
|
Add mdeleg tests
|
2019-03-23 11:41:10 +01:00 |
|
Dolu1990
|
9139b4d269
|
Restore all tests
|
2019-03-22 18:03:35 +01:00 |
|
Dolu1990
|
597336b491
|
MMU sum/mxr tested and ok, all seem finen
|
2019-03-22 17:11:55 +01:00 |
|
Dolu1990
|
f7b793b7bf
|
Add SSTATUS.SUM/MXR feature, need testing
|
2019-03-22 15:49:36 +01:00 |
|
Dolu1990
|
e4cdc2397a
|
MMU pass all test, need to and SUM and MXR and it's all ok
|
2019-03-22 14:52:49 +01:00 |
|
Dolu1990
|
2b458fc642
|
Added MMU superpage support, pass MMU tests
|
2019-03-22 12:23:47 +01:00 |
|
Dolu1990
|
af2acbd46e
|
Got the new MMU design to pass simple tests #60
|
2019-03-22 01:10:17 +01:00 |
|
Tom Verbeure
|
59a2817e5c
|
Update DecoderSimplePlugin manual.
|
2019-03-21 05:53:27 +00:00 |
|
Tom Verbeure
|
3f5605f22e
|
Fix table.
|
2019-03-21 05:36:30 +00:00 |
|
Tom Verbeure
|
02a6312912
|
Update IBusCachedPlugin manual.
|
2019-03-21 05:34:15 +00:00 |
|
Tom Verbeure
|
b7ddd02fc6
|
IBusSimplePlugin README.
|
2019-03-21 05:17:07 +00:00 |
|
Dolu1990
|
ea56481ead
|
Add supervisor CSR in the riscv golden model
|
2019-03-20 23:26:08 +01:00 |
|
Dolu1990
|
7cbe399f1f
|
Fix some supervisor CSR access
|
2019-03-20 23:25:52 +01:00 |
|
Dolu1990
|
6f2e5a0eb7
|
goldenmodel Implement some of the supervisor CSR
|
2019-03-20 20:28:04 +01:00 |
|
Dolu1990
|
39b2803914
|
Fix some CsrPlugin flags issues
|
2019-03-20 20:27:47 +01:00 |
|
Dolu1990
|
6c2fe934fd
|
Bring changes and fixies from @kgugala @daveshah1. Thanks guys !
|
2019-03-20 16:27:35 +01:00 |
|
Dolu1990
|
130a69eeae
|
Pass regressions machinemode with CSR config including Supervisor
|
2019-03-20 14:14:59 +01:00 |
|
Dolu1990
|
d205f88fb8
|
riscv golden model and RTL pass all current regressions
add RVC into the linux config
|
2019-03-20 12:17:43 +01:00 |
|
Dolu1990
|
3c66f7c58a
|
goldenmodel now pass more machine mode CSR tests
|
2019-03-20 11:46:27 +01:00 |
|
Dolu1990
|
ee402ec5dc
|
clearning
|
2019-03-20 01:16:39 +01:00 |
|
Dolu1990
|
3a38fe4130
|
Add mmu regresion blank project
|
2019-03-20 01:13:05 +01:00 |
|
Dolu1990
|
ccc3b63d7c
|
Enable golden model check for all regressions
Need to implement missing CSR of the golden model
|
2019-03-20 01:12:03 +01:00 |
|
Dolu1990
|
8f22365959
|
Disable MMU in machine mode
|
2019-03-19 22:21:30 +01:00 |
|
Dolu1990
|
46f10bacb2
|
Merge pull request #64 from tomverbeure/MulSimple
MulSimplePlugin
|
2019-03-19 20:39:28 +01:00 |
|
Dolu1990
|
3fbc2f4458
|
Fix generation
|
2019-03-19 20:29:28 +01:00 |
|
Dolu1990
|
915db9d6c9
|
cleaning
|
2019-03-18 20:50:19 +01:00 |
|
Dolu1990
|
001ca45c57
|
Add cachless dBus IBus access right checks
|
2019-03-18 12:52:22 +01:00 |
|
Dolu1990
|
c490838202
|
Added MMU support into cacheless DBus IBus plugins (for testing purposes)
Probably full of bugs, need testing
|
2019-03-18 12:17:43 +01:00 |
|
Dolu1990
|
ffa489d211
|
hardware refilled MmuPlugin wip
|
2019-03-17 21:06:47 +01:00 |
|
Tom Verbeure
|
b63395435f
|
SimpleMul core.
|
2019-03-16 15:44:18 +00:00 |
|
Tom Verbeure
|
5bc53c08ce
|
Merge branch 'master' of https://github.com/SpinalHDL/VexRiscv into MulSimple
|
2019-03-16 15:39:07 +00:00 |
|
Dolu1990
|
03663ce91a
|
Move unreleased SpinalHDL
|
2019-03-15 17:35:31 +01:00 |
|
Dolu1990
|
9a61ff8347
|
Merge remote-tracking branch 'origin/dev'
|
2019-03-10 11:14:09 +01:00 |
|
Dolu1990
|
2e0b63bc67
|
SpinalHDL 1.3.2
|
2019-03-10 11:12:43 +01:00 |
|
Dolu1990
|
bad60f39cd
|
Fix Decoding benchmark
|
2019-03-10 11:12:32 +01:00 |
|
Dolu1990
|
434793711b
|
fix part of #59
|
2019-02-26 17:26:42 +01:00 |
|
Dolu1990
|
b9922105f0
|
Fix readme demo path
|
2019-02-26 17:22:13 +01:00 |
|
Dolu1990
|
e0214056ce
|
Merge pull request #58 from mithro/patch-1
Fix image in README.
|
2019-02-23 09:22:38 +01:00 |
Tim Ansell
|
7594cbd902
|
Fixing images in README in iCE40-hx8k_breakout_board_xip directory too.
|
2019-02-22 14:57:07 -08:00 |
|
Tim Ansell
|
5c6cc29304
|
Fixing other image.
|
2019-02-22 14:55:18 -08:00 |
|
Tim Ansell
|
c9f4a09de0
|
Fix image in README.
|
2019-02-22 14:52:09 -08:00 |
|
Dolu1990
|
e0c8ac01d2
|
Add custom external interrupts
|
2019-02-03 15:20:34 +01:00 |
|
Dolu1990
|
11f55359c6
|
IBusCache can now avoid injectorStage in singleStage mode
|
2019-01-30 01:37:47 +01:00 |
|
Dolu1990
|
56e3321394
|
cpp regresion now print the time of failure
|
2019-01-30 01:36:24 +01:00 |
|
Dolu1990
|
285f6bb6ac
|
Update README.md
Remove JDK constraints
|
2019-01-29 12:35:12 +01:00 |