Dolu1990
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c2b9544794
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Allow iBusCached plugin to be used when no memory stage is present
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2018-11-24 13:37:53 +01:00 |
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Dolu1990
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2d8d3d0566
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Update readme
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2018-11-22 22:49:16 +01:00 |
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Dolu1990
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f18696357f
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SpinalHDL 1.2.2
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2018-11-22 22:45:07 +01:00 |
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Dolu1990
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0086de9e36
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Fix CsrPlugin catch illegalAccess
Add dhrystone optimized divider
cleaning
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2018-11-20 19:39:17 +01:00 |
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Dolu1990
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75d4d049d7
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Add shadow regfile
various cleaning
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2018-11-16 17:06:11 +01:00 |
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Dolu1990
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cc48fc7403
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add fenceiGenAsANop
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2018-11-13 15:17:35 +01:00 |
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Dolu1990
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0d92a5e5cd
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Add many little options to reduce area
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2018-11-12 14:14:34 +01:00 |
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Dolu1990
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fb9ea11a5e
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Allow VexRiscv to suppress the memory and the writeback stage, allowing to go downto a 2 stage CPU (FETCH_DECODE, EXECUTE)
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2018-11-09 05:41:43 +01:00 |
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Dolu1990
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b12e15b112
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branch/csr/muldiv minor improvments
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2018-11-07 19:27:49 +01:00 |
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Dolu1990
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b7f3ee5e06
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Fix CsrPlugin pipelined option
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2018-11-05 16:22:41 +01:00 |
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Dolu1990
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662d76e3aa
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csrPlugin : avoid using ALU to get SRC1 (which was useless)
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2018-11-03 11:29:30 +01:00 |
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Dolu1990
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978232fd63
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Optimise div iterative plugin done signal
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2018-11-03 11:12:37 +01:00 |
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Dolu1990
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c8ac214097
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Optimize CSR
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2018-10-28 02:18:27 +02:00 |
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Dolu1990
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51de2b5820
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SimpleBusInterconnect now adapte address width
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2018-10-28 02:18:08 +02:00 |
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Dolu1990
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00bf84b7f8
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Add SimpleBusInterconnect
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2018-10-25 23:47:05 +02:00 |
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Dolu1990
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4ed4af6a3e
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SrcPlugin add decodeAddSub option
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2018-10-24 01:28:37 +02:00 |
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Dolu1990
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372063582c
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Improve CsrPlugin CombinatorialPaths
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2018-10-23 19:07:08 +02:00 |
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Dolu1990
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7096c63d50
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Add more SimpleBus utilies
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2018-10-23 17:46:31 +02:00 |
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Dolu1990
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7c0f2dc713
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Add SimpleBus object
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2018-10-20 12:39:30 +02:00 |
Morard Dany
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85e696b286
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CsrPlugin : Add mtvecModeGen
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2018-10-16 14:53:41 +02:00 |
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Dolu1990
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1e64d71609
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Merge remote-tracking branch 'origin/Supervisor' into dev
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2018-10-16 13:09:17 +02:00 |
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Dolu1990
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905abd5aaa
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Add wfiGenAsWait and wfiGenAsNop
CsrPlugin cleaning
Much cleaning in general
Zephyr is running
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2018-10-16 13:07:30 +02:00 |
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Dolu1990
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f903df4b66
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sync
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2018-10-12 17:13:54 +02:00 |
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Dolu1990
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2b29690010
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Clean branch plugin lsb bit calculation
BranchPlugin doesn't try anymore to catch exception when RVC is on
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2018-10-12 12:24:52 +02:00 |
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Dolu1990
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eea92154ae
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fetcher force PC LSB to be zero
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2018-10-12 12:02:52 +02:00 |
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Dolu1990
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0b8f6f6ed4
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Fix broken C.LWSP reference_output
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2018-10-12 12:02:02 +02:00 |
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Dolu1990
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594f7a8bf2
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Seem to pass all risc-v compliance tests, excepted the C.LWSP which is a broken test
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2018-10-11 22:19:17 +02:00 |
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Dolu1990
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8c25e73b9d
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Fix DIV negative values divided by zero
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2018-10-11 22:18:21 +02:00 |
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Dolu1990
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c26b7e15cf
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BranchPlugin exceptions are now risc-v compliance alligned
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2018-10-11 17:56:49 +02:00 |
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Dolu1990
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8b1a4a2717
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Add RISCV compliance regression test, need to fix I-MISALIGN_JMP-01 mtval
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2018-10-11 00:25:39 +02:00 |
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Dolu1990
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40d85b8c70
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Add fenceiGenAsAJump into BranchPlugin
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2018-10-10 21:13:21 +02:00 |
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Dolu1990
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68f1ff3222
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Add CsrPlugin ebreak support
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2018-10-10 19:23:04 +02:00 |
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Dolu1990
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0662cc2797
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Add GenMicro experiment to reduce ice40 area usage.
IBusSimplePlugin now require cmdFork parameters to be set (no default)
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2018-10-03 22:08:57 +02:00 |
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Dolu1990
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48bff80653
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rework fetchPc to optionaly share the pcReg with the stage(1)
IBusSimplePlugin now implement cmdForkPersistence option
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2018-10-03 16:24:10 +02:00 |
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Dolu1990
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c61f17aea3
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Fetcher/IBusSimplePlugin wip
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2018-10-03 01:02:22 +02:00 |
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Dolu1990
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0ada869b2d
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regression golden ref regfile is now sync with trl boot's random values
wip
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2018-10-01 16:14:21 +02:00 |
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Dolu1990
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65a8d84d30
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Introduce HAS_SIDE_EFFECT Stageable to solve sensitive instruction squeduling
(uncached DBus TODO)
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2018-10-01 12:13:05 +02:00 |
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Dolu1990
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7770eefa3b
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wip
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2018-09-30 12:57:08 +02:00 |
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Dolu1990
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39c6bc11d6
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Pass basic regression again
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2018-09-29 19:04:20 +02:00 |
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Dolu1990
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5ad7c39f47
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wip
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2018-09-29 12:04:58 +02:00 |
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Dolu1990
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37a1970ad6
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wip
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2018-09-28 16:02:33 +02:00 |
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Dolu1990
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32cf90a162
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Merge remote-tracking branch 'origin/dev' into Supervisor
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2018-09-27 22:16:49 +02:00 |
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Dolu1990
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992c21ddd1
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fix travis
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2018-09-27 19:06:33 +02:00 |
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Dolu1990
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9a3510f63d
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Map all supervisor registers
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2018-09-27 19:03:57 +02:00 |
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Dolu1990
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acd1ca422a
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wip
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2018-09-27 18:24:40 +02:00 |
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Dolu1990
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a2d3cfbfc1
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Remove unused file
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2018-09-27 00:56:20 +02:00 |
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Dolu1990
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6dde73f97c
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Murax demo with XIP is now fully defined in SpinalHDL
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2018-09-27 00:55:30 +02:00 |
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Dolu1990
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aff436ddcf
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Sync with SpinalHDL head
Add mmu test into the dhrystone regression command
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2018-09-24 18:31:33 +02:00 |
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Dolu1990
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1e3b75ef1d
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xip typo
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2018-09-23 22:06:21 +02:00 |
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Dolu1990
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86efb75f6a
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rework fetcher
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2018-09-23 22:05:53 +02:00 |