Dolu1990
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c16f2ed787
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Add probes in SmpCluster sim
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2020-05-04 12:54:28 +02:00 |
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Dolu1990
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b0f7f37ac8
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D$ now support memDataWidth > 32
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2020-05-04 12:54:16 +02:00 |
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Dolu1990
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93b386e16e
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litex smp cluster now use OO decoder
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2020-05-02 23:44:58 +02:00 |
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Dolu1990
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f0745eb0d9
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update SMP line size to 64 bytes
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2020-05-02 23:44:27 +02:00 |
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Dolu1990
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09ac23b78f
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Fix SMP fence lock when 4 stages CPU
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2020-05-01 12:45:16 +02:00 |
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Dolu1990
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f5f30615ba
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Got litex SMP cluster to work on FPGA
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2020-05-01 11:14:52 +02:00 |
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Dolu1990
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dc0da9662a
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Update SMP fence (final)
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2020-05-01 11:14:11 +02:00 |
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Dolu1990
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7c50fa6d55
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SmpCluster now use i$ line of 64 bytes
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2020-04-29 14:03:00 +02:00 |
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Dolu1990
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9e9d28bfa6
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d$ now implement consistancy hazard by using writeback redo
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2020-04-29 14:02:41 +02:00 |
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Dolu1990
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86e0cbc1f3
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I$ with memDataWidth > cpuDataWidth now mux memWords into cpuWords before the decode stage by default. Add twoCycleRamInnerMux option to move that to the decode stage
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2020-04-29 13:59:43 +02:00 |
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Dolu1990
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7b80e1fc30
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Set SMP workspace to use i$ memDataWidth of 128 bits
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2020-04-28 22:11:41 +02:00 |
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Dolu1990
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eee9927baf
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IBusCachedPlugin now support memory data width multiple of 32
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2020-04-28 22:10:56 +02:00 |
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Dolu1990
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23b8c40cab
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update travis verilator
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2020-04-28 16:19:00 +02:00 |
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Dolu1990
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03a0445775
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Fix SMP for configuration without writeback stage.
Include SMP core into the single core tests regressions
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2020-04-28 15:50:20 +02:00 |
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Dolu1990
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4a49b23636
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Fix regression
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2020-04-28 14:38:27 +02:00 |
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Dolu1990
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3ba509931c
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Add VexRiscvSmpLitexCluster with the required pipelining to get proper FMax
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2020-04-27 17:38:06 +02:00 |
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Dolu1990
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5fd0b220cd
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CsrPlugin add openSbi config
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2020-04-27 17:37:30 +02:00 |
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Dolu1990
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0c59dd9ed3
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SMP fence now ensure ordering for all kinds of memory transfers
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2020-04-27 17:37:15 +02:00 |
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Dolu1990
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3fb123a64a
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fix withStall
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2020-04-21 21:20:54 +02:00 |
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Dolu1990
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3885e52bb7
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Merge remote-tracking branch 'origin/dev' into smp
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2020-04-21 17:21:48 +02:00 |
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Dolu1990
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4016b1fc52
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Add sbt assembly
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2020-04-21 17:18:08 +02:00 |
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Dolu1990
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056bf63866
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Add more consistancy tests
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2020-04-21 16:03:03 +02:00 |
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Dolu1990
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b389878d23
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Add smp consistency check, fix VexRiscv invalidation read during write hazard logic
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2020-04-21 12:18:10 +02:00 |
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Dolu1990
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0e55caacab
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deduplicae VexRiscv wishbone
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2020-04-21 10:33:51 +02:00 |
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Dolu1990
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b383b4b98b
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Add commented usage of fromXilinxBscane2
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2020-04-20 12:13:12 +02:00 |
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Dolu1990
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8e8b64feaa
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Got full linux / buildroot to boot in 4 cpu config
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2020-04-19 19:49:26 +02:00 |
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Dolu1990
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a1b6353d6b
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workaround AMO LR/SC consistancy issue, but that need a proper fix
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2020-04-19 19:48:57 +02:00 |
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Dolu1990
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ad2d2e411a
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Add tap less debug plugin bridges
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2020-04-19 17:56:33 +02:00 |
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Dolu1990
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af128ec9eb
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revert to 4 cpu
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2020-04-18 01:27:35 +02:00 |
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Dolu1990
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4a49e6d91f
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initialize the clint in sim
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2020-04-18 01:26:31 +02:00 |
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Dolu1990
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befecc7ed6
|
cleaning
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2020-04-18 00:51:57 +02:00 |
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Dolu1990
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8c0e534c6b
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Add openSBI test, seem to work fine
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2020-04-18 00:51:47 +02:00 |
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Dolu1990
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ebe070f9dd
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Update README.md
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2020-04-17 19:58:54 +02:00 |
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Dolu1990
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d5a52caab8
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fix smp test barrier
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2020-04-16 17:27:27 +02:00 |
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Dolu1990
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d88d04dbc4
|
More SMP tests (barrier via AMO and LRSC)
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2020-04-16 15:23:25 +02:00 |
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Dolu1990
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fd52f9ba50
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Add smp.bin
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2020-04-16 02:22:18 +02:00 |
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Dolu1990
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73c21177e5
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Add VexRiscvSmpCluster, seem to work on simple case
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2020-04-16 01:30:03 +02:00 |
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Dolu1990
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b9ceabf128
|
few fixes
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2020-04-16 01:29:13 +02:00 |
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Dolu1990
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46207abbc4
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dataCache now implement invalidation sync
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2020-04-16 01:28:38 +02:00 |
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Dolu1990
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a00605b10c
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fix Briey verilator
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2020-04-13 13:01:12 +02:00 |
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Dolu1990
|
467a2bc488
|
refactor DBus invalidation, and add invalidation enable
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2020-04-11 19:06:22 +02:00 |
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Dolu1990
|
abbfaf6bcf
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regression : restore normal invalidation setup
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2020-04-10 18:58:03 +02:00 |
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Dolu1990
|
4a9b8c1f72
|
improve invalidation read during write hazard logic
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2020-04-10 14:44:28 +02:00 |
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Dolu1990
|
0ad0f5ed3f
|
Add d$ invalidation tests
fix d$ invalidation, linux OK
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2020-04-10 14:28:16 +02:00 |
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Dolu1990
|
f71f360e32
|
Add SMP synthesis
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2020-04-10 14:27:39 +02:00 |
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Dolu1990
|
296cb44bc4
|
Add hardware AMO support using LR/SC exclusive
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2020-04-09 20:12:37 +02:00 |
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Dolu1990
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1d0e180e1d
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Add GenTwoStage config and UltraScale synthesis
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2020-04-09 20:11:56 +02:00 |
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Dolu1990
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861df664cf
|
clean some AMO stuff
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2020-04-08 18:48:01 +02:00 |
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Dolu1990
|
6922f80a87
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DataCache now implement fence operations
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2020-04-08 18:12:13 +02:00 |
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Dolu1990
|
9e1817a280
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fix DataCache for config without invalidation
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2020-04-07 20:05:24 +02:00 |