2c60861929
Merge pull request #232 from antmicro/jboc/init-mr
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init: make the write leveling MR bit configurable
2021-02-02 09:36:46 +01:00
83b31f4f71
Merge pull request #231 from antmicro/jboc/module-timings
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Allow to pass all module timings in the format (ck, ns)
2021-02-02 09:28:30 +01:00
9d80829e47
Merge pull request #230 from antmicro/jboc/test-init-diff
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test: improve error messages when comparing files in test_init.py
2021-01-30 21:47:19 +01:00
17db7573fb
Merge pull request #229 from craigjb/port_width
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Add customizable standalone user port data widths
2021-01-30 21:45:58 +01:00
b3ce582891
test: update ddr3 and ddr4 reference headers to new MR_WLVL defines
2021-01-29 12:49:19 +01:00
f9d39da2e1
init: avoid unnecessary newlines when adding MR_WLVL defines
2021-01-29 12:48:24 +01:00
e7ca72b22f
fix Python init header generation
2021-01-29 12:45:06 +01:00
12d66c119d
phy/model: update DFITimingsChecker to new SDRAMModule timings format
2021-01-29 11:22:33 +01:00
436bfc4fbd
modules: extend parsing of timings to always allow (ck, ns) format
2021-01-29 11:16:16 +01:00
2f5784432d
phys: improve handling of required/optional command pads and make cke/odt optional on all phys.
2021-01-29 09:28:33 +01:00
a1e7d805ec
test: improve error messages when comparing files in test_init.py
2021-01-28 17:44:13 +01:00
bb85ce8f0f
init: make the write leveling MR bit configurable
2021-01-28 16:02:46 +01:00
5a114be7e5
phy/ecp5ddrphy: add clk_polarity parameter to allow inverting clk polarity (for boards with clk_p/n swapped).
2021-01-27 18:36:53 +01:00
562cd3207c
Merge pull request #228 from garytwong/IS43TR16256A
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modules: add IS43TR16256A support.
2021-01-27 08:00:06 +01:00
af9abd6ec9
phy/ecp5ddrphy: remove dm_remapping introduce for VexRiscv-SMP on OrangeCrab: we can now use Wishbone/L2.
2021-01-25 11:54:15 +01:00
5c32dc71c4
Add customizable standalone user port data widths
2021-01-24 21:58:46 -07:00
537e118c6b
modules: add IS43TR16256A support.
2021-01-22 12:30:29 -07:00
ab2423e3dd
litedram_gen: add initial Ultrascale+ support with XCU1525 .yml example.
2021-01-22 12:04:24 +01:00
0127937215
phy/usddrphy: simplify tCK reference by using a specific ODELAYE3 in FIXED mode and keep the PHY in reset by default.
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Keeping the PHY in reset by default was not possible previously due to the ODELAYE3 configuration
that was lost on reset. Using a specific ODELAYE3 in FIXED mode allow keeping the PHY in reset at
startup.
2021-01-21 18:18:39 +01:00
a91883db23
phy/ecp5ddrphy: add configurable cmd_delay.
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Allow adding a delay on Clock/Commands. Delay is manual for now but could be
automated in the future if useful (as done on 7-series/Ultrascale(+)).
2021-01-12 18:42:54 +01:00
53e98f75be
phy/ecp5ddrphy: remplace dq_i DELAYF with DELAYG.
2021-01-12 17:32:02 +01:00
919a613733
phy/ecp5ddrphy: use nphases on DFI.
2021-01-12 17:24:10 +01:00
c29c898af4
platforms/targets: switch to LiteX-Boards.
2021-01-04 14:11:32 +01:00
ec1f34f5f9
phy/ecp5/s7/us: allow user to provide cl/cwl instead of default values.
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One some hardware, forcing cl or/and cwl to non-default values can provide
better results.
2021-01-04 13:22:18 +01:00
d4c5c7cef8
phy/gensdrphy: compute default cl from sys_clk_freq (similar what is already done on other PHYs).
2021-01-04 11:31:13 +01:00
e683b48c4a
common: rename get_cl_cw function to get_default_cl_cwl (and provide retro-compat) and add get_default_cl, get_default_cwl functions.
2021-01-04 11:04:04 +01:00
e9479cca83
phy/gensdrphy: remove unused cmd_latency parameter.
2021-01-04 10:53:47 +01:00
87f95f8442
Merge pull request #226 from mdpye/MT48LC32M8
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modules: add MT48LC32M8 SDR module
2021-01-03 22:13:19 +01:00
ec37a6353b
modules: add MT48LC32M8 SDR module
2020-12-31 13:10:24 +00:00
103072c68a
test/reference: update.
2020-12-17 18:21:53 +01:00
d8eccebbbc
ci: update RISC-V GCC install.
2020-12-17 17:13:58 +01:00
33f3aa55e5
phy/ecp5ddrphy: add DM remapping capability.
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Required on OrangeCrab that has LDM/UDM swapped.
2020-12-16 11:49:33 +01:00
596615a238
bench/common: add progress to load_rom.
2020-12-10 19:22:46 +01:00
a87c468afa
bench: use --sys-clk-freq=xy to reconfigure frequency and fix Ultrascale.
2020-12-10 19:06:19 +01:00
efb1975d00
bench/arty: add missing eth clock.
2020-12-10 13:43:31 +01:00
75f87538a5
bench: use common load_bios function.
2020-12-10 11:21:21 +01:00
ea63480253
bench/targets: add identifier.
2020-12-10 11:12:45 +01:00
c472499131
bench/targets: add optional analyzer on all test targets.
2020-12-10 08:44:35 +01:00
62845f1ec9
phy/usddrphy: update header with 1333, 1866 MT/s.
2020-12-10 08:44:05 +01:00
496cd27a3d
phy/s7/usddrphy: set default cmd_latency to 0.
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Now that we are restricting cmd/clk scan in liblitedram, cmd_latency=0 seems
to be workin for all configurations.
2020-12-08 10:05:09 +01:00
af979bbd31
ci: install RISC-V GCC (requires for LiteDRAM standalone core examples).
2020-11-24 19:48:56 +01:00
68cd462bd4
ci: migrate from Travis CI to Github Actions.
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Only covers unit-tests for now, Verilator simulation and benchmarks still need to be adapted.
2020-11-24 13:43:43 +01:00
b6252345af
test/reference: update ddr4.
2020-11-17 17:12:02 +01:00
6b9f1bd0d8
ddr4: Enable Data Mask for DDR4 memory and invert its polarity.
2020-11-17 15:06:58 +01:00
1117068595
phy/s7ddrphy: make pads.dm optional (some boards have dm forced to ground).
2020-11-12 19:15:49 +01:00
431e563a39
common: move cmd/wdata/rdata descriptions and add minimal description of signals.
2020-11-09 12:06:02 +01:00
c83e10dafe
bench: cleanup clocking on Ultrascale targets.
2020-11-06 16:14:22 +01:00
9a50f6ece6
bench/ddr4_mr_gen.py: change default cl to 9 (cl value for sys_clk_freq=125e6).
2020-11-06 14:44:36 +01:00
4d1f4d5052
bench/xcu1525: use specific output_dir per channel (to allow // build of bitstreams for the different channels).
2020-11-06 10:47:26 +01:00
0890908a63
bench/xcu1525: rename ddram_channel arg to channel (since it's a dram specific design).
2020-11-06 10:36:56 +01:00
enjoy-digital
Jędrzej Boczar
Craig Bishop
Gary Wong
Nathaniel R. Lewis