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litedram
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558 Commits 5 Branches 14 Tags 5.7 MiB
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558 Commits

Author SHA1 Message Date
Florent Kermarrec 7eee80da19 frontend/ecc: add description, rename dec signal to ded 2019-01-04 08:44:05 +01:00
Florent Kermarrec 14c6062b00 core/crossbar: remove "ROW_COL_BANK" address_mapping (need to be simulated) 2018-12-28 11:10:53 +01:00
Florent Kermarrec 180b3d2cc1 modules: adjust MT48LC16M16 timings 2018-12-27 22:25:59 +01:00
Florent Kermarrec 906edf1917 phy/gensdrphy: make cke/dm optional. 2018-12-23 23:10:04 +01:00
Florent Kermarrec 81fa19e58d phy/usddrphy: fix DRC REQP-1665. 
When the ODELAYE3 ODELAYE3 DELAY_TYPE is FIXED, the RST pin should be GND.
 2018-12-19 11:37:06 +01:00
Florent Kermarrec c275755473 phy/usddrphy: add iodelay_clk_freq parameter 2018-12-19 10:43:17 +01:00
Florent Kermarrec 62a31de21f phy: rename KUSDDRPHY to USDDRPHY since compatible with Kintex/Virtex Ultrascale 2018-12-18 11:31:41 +01:00
Florent Kermarrec e91366cd31 frontend/axi: use buffered SyncFIFO on datapath (reduce resource usage) 2018-12-18 10:57:05 +01:00
Florent Kermarrec da6fc8c39b README: add Kintex Ultrascale PHY 2018-12-17 16:08:57 +01:00
Florent Kermarrec 8993e8b798 core/refresher: fix refresh regression 2018-12-17 15:31:27 +01:00
Florent Kermarrec 83f763f7b8 phy: replace wdly_dqs_taps with half_sys8x_taps (similar to what is implemented on 7-series) 2018-12-17 11:42:13 +01:00
Florent Kermarrec 28b7d3264c phy/kusddrphy: use rdly_dq_bitslip_rst CSR for bitslip reset 2018-12-17 11:04:45 +01:00
Florent Kermarrec 1ece2ca7b7 phy/dfi: set act_n reset value to 1 2018-12-17 08:56:00 +01:00
Florent Kermarrec 057200665f phy/kusddrphy: remove ResetSignal on ODELAYE3/ISERDESE3 that are dynamically adjusted, reduce sys latency 2018-12-13 18:52:54 +01:00
Florent Kermarrec 57ebcc53ca sdram_init/ddr4: enable dll 2018-12-13 18:51:12 +01:00
Florent Kermarrec 7a2ff338f5 sdram_init/get_sdram_phy_py_header: generate mr1 value, fix init_sequence identation 2018-12-13 16:30:29 +01:00
Florent Kermarrec 33ff34b622 core/refresher: use self.sync to fix build (verilog wire vs reg...) 2018-12-07 17:46:43 +01:00
Florent Kermarrec 8419f2846d core: split refresher, expose it and allow it to be reloaded externally. 2018-12-07 10:15:54 +01:00
Florent Kermarrec 8ec0bc678e modules: improve the way we define DDR4 banks/groups 2018-12-06 21:16:37 +01:00
Florent Kermarrec 1618a7636a phy: add KUSDDRPHY to __init__.py 2018-12-06 21:15:47 +01:00
Florent Kermarrec d6350d9fec test/test_axi: reduce rand_level on writes 2018-12-05 11:44:38 +01:00
Florent Kermarrec 282b60e94c frontend/axi: simplify LiteDRAMAXI2NativeW logic 
Accept the Address/Data only if:
- Address & Data request are *both* valid.
- Data buffer is not full.
 2018-12-05 11:44:23 +01:00
Florent Kermarrec 6778c72665 test/test_axi: cleanup, all tests passings. 2018-12-03 08:01:33 +01:00
Florent Kermarrec ebb1d3c762 frontend/axi/LiteDRAMAXI2NativeW: be sure that we already have the data before sending the command to the controller 2018-12-01 12:11:22 +01:00
Florent Kermarrec 0d5e5543fb frontend/axi: expose aw_burst2beat/ar_burst2beat 2018-11-30 12:32:15 +01:00
Florent Kermarrec da65a804be frontend/axi: expose w_buffer/r_buffer (can be useful for debug) 2018-11-30 11:59:22 +01:00
Florent Kermarrec 7f5d749c6b test: add missing +x 2018-11-30 11:58:45 +01:00
Florent Kermarrec 7ef4869db9 test/test_axi: also add randomness on rdata.valid and wdata.ready 2018-11-30 11:22:04 +01:00
Florent Kermarrec 3db68cdd50 test/test_axi/axi2native: add tests for each randomness parameters (ease finding regressions issues) 2018-11-30 10:40:45 +01:00
Florent Kermarrec 190b1bd01f test/test_axi/axi2native: add finer control on randomness 2018-11-30 09:40:13 +01:00
Florent Kermarrec 4f137b9334 test/test_axi/axi2native: add random on len, just use writes as reads 2018-11-29 23:45:38 +01:00
Florent Kermarrec 2a799e4f1d test/test_axi: set size on axi2native test 2018-11-29 23:45:31 +01:00
Florent Kermarrec e70d77e76e phy/s7dddrphy: fix nphases = 2 (same code can be shared between nphases = 2 and nphases = 4) 2018-11-29 16:56:23 +01:00
Florent Kermarrec 170b3dc67d frontend/wishbone: set aw/ar size on LiteDRAMWishbone2AXI 2018-11-26 10:37:28 +01:00
Florent Kermarrec 9a255062e0 frontend/wishbone: fix wishbone.err on LiteDRAMWishbone2AXI 2018-11-26 08:56:00 +01:00
Florent Kermarrec bc6a3f220a examples/sim/sim/py: remove apb interface 2018-11-17 09:30:58 +01:00
Florent Kermarrec e7e4bc527f examples/sim: add ddr3 micron model 2018-11-17 09:20:34 +01:00
Florent Kermarrec f219693635 examples: add simulation 2018-11-17 09:19:52 +01:00
Florent Kermarrec 30d9a3e2c2 modules: add MT40A1G8 DDR4 2018-11-13 11:05:38 +01:00
Florent Kermarrec 4459bd25ed frontend/axi: same condition to connect connect wdata.we and wdata 2018-11-13 10:37:54 +01:00
Florent Kermarrec d10e2e9d97 core: make address_mapping a controller setting 2018-11-13 09:18:46 +01:00
Florent Kermarrec 7973b7d361 frontend/axi: emits the write command only if we have the write data 2018-11-12 19:17:31 +01:00
Florent Kermarrec 6fa891d5d6 frontend/axi: fix write response for bursts 2018-11-12 18:02:54 +01:00
Florent Kermarrec 93e8510f55 test/test_axi: add bursts to axi2native 2018-11-12 18:00:28 +01:00
Florent Kermarrec e27fbc2430 test/test_axi: move definitions to top and make Access herit from Burst 2018-11-12 13:09:05 +01:00
Florent Kermarrec 4470f32ef8 test/test_axi: change order of the tests 2018-11-12 12:59:19 +01:00
Florent Kermarrec 070cc26994 test/test_axi: use separate generator for writes cmd/data 2018-11-12 12:58:19 +01:00
Florent Kermarrec 127e9285a3 frontend/wishbone: simplify LiteDRAMWishbone2Native code (resource usage almost the same) 2018-11-09 15:44:49 +01:00
Florent Kermarrec ca82ac18d0 frontend/wishbone: add LiteDRAMWishbone2AXI 2018-11-09 15:32:49 +01:00
Florent Kermarrec 3586e157f2 frontend/axi: improve len/size comment (-1), set default id_width to 1 2018-11-09 15:29:31 +01:00