b145b0c338
frontend/axi: fix write response implementation
2018-09-18 15:24:41 +02:00
d23dbf6e57
phy: add nranks to all phys
2018-09-17 09:07:09 +02:00
461b076624
frontend/ecc: add ecc adapter
2018-09-16 01:01:45 +02:00
c84b58735a
frontend: add initial ecc code (still need to be integrated)
...
Works but all combinatorial, will maybe need to be pipelined
2018-09-15 23:37:59 +02:00
a8d26724dd
phy/s7ddrphy_halfrate_bl8: don't generate dqs pre/post-amble, needs simulation
2018-09-15 02:22:12 +02:00
5719d71ace
phy/s7ddrphy_halfrate_bl8: fix cs_n
2018-09-15 00:47:33 +02:00
36fa324291
core/multiplexer: fix regression (introduced by multirank support)
2018-09-12 07:14:59 +02:00
42d0e5bbaa
core/multiplexer: add more information on odt fixme
2018-09-10 16:34:18 +02:00
919b756261
phy/model: pass nranks to Interface
2018-09-10 15:17:07 +02:00
f5c7b61704
multirank: set default nranks to 1 if not specified
2018-09-10 15:16:46 +02:00
f3d403f1e0
s7ddrphy: fix typo (reset_n --> cs_n)
2018-09-10 04:44:35 +02:00
37f1decfb2
multirank: one cs_n/cke/odt/clk per rank
2018-09-09 14:32:15 +02:00
3e17d18b0c
phy: add halfrate_bl8 variant for s7ddrphy
2018-09-09 03:30:18 +02:00
412e9a5c51
Merge pull request #38 from enjoy-digital/multirank
...
Multirank
2018-09-09 02:03:20 +02:00
8ddc6c735d
drive odt of all ranks, fixes and test non regression with 1 rank
2018-09-09 01:52:24 +02:00
d9c243037a
Merge pull request #36 from JohnSully/timing_1
...
Fix failing timing
2018-09-08 13:17:26 +02:00
efd7a47890
Fix failing timing
2018-09-07 22:12:24 -04:00
d4f434da3d
dfii: send command to all ranks
2018-09-07 18:40:46 +02:00
b1c2739305
initial multirank support (nbankmachines = nranks * (2**bankbits))
...
To see:
Configure the 2 ranks. (init commands, leveling)
How to drive ODT?
Pipeline stall while switching ranks?
2018-09-07 18:34:08 +02:00
cc481be81f
examples: add sdram_rank_nb and user_ports_id_width
2018-09-07 17:55:46 +02:00
849b1f6c35
frontend/axi: generate rlast signal
2018-09-06 11:11:17 +02:00
1fa73e4718
test: update
2018-09-06 11:10:45 +02:00
7b61b68f68
sdram_init: min value for wr is 5
2018-09-05 23:40:04 +02:00
1652ab95c8
examples/litedram_gen: fix address width of axi ports (addressing in bytes not words)
2018-09-05 09:13:47 +02:00
1e64b7f492
examples/litedram_gen: expose resp signals to user
2018-09-05 08:51:27 +02:00
700f76c599
frontend/axi: add resp signals
2018-09-05 08:50:28 +02:00
47fed1b254
frontend/axi: add last limitation
2018-09-05 08:33:49 +02:00
de69867995
examples/litedram_gen: expose last signals to user
2018-09-05 08:32:49 +02:00
e8bd782999
examples/litedram_gen: expose burst signals to user
2018-09-05 08:31:57 +02:00
e1598ceee8
phy/s7ddrphy: fix BL8 assert
2018-09-04 09:34:10 +02:00
ebba39d928
README: update
2018-09-03 14:18:35 +02:00
e528e92b9b
phy/s7ddrphy: add assertion to avoid generating 1:2 controller with DDR3 (needs BL8 support in the PHY)
2018-09-03 14:06:04 +02:00
6017e7a763
phy/s7ddrphy: fix dqs_sys_latency for DDR2
2018-09-03 12:21:04 +02:00
7b427391bd
phy/s7ddrphy: simplify cmd/dat phases computation and remove restrictions.
...
The real restrictions are:
- dat_phase = sys_latency*nphases - cas_latency (at least for writes, for read we can compensate that with bitslip)
- dat_phase != cmd_phase.
2018-09-03 11:15:37 +02:00
614861891e
phy/s7ddrphy: use dict in get_cl_cw function
2018-09-03 10:18:54 +02:00
5e4dca9a7b
add examples with standalone cores for arty and genesys2
2018-08-31 23:20:47 +02:00
dce4edee97
README: update
2018-08-31 08:25:05 +02:00
f6797a16bb
test/test_axi: add burst wrap test and fix code
2018-08-29 18:47:40 +02:00
47988d8cd3
frontend/axi: remove alignment limitation since we are in fact supporting unaligned transfers as described in the specification.
2018-08-29 18:08:50 +02:00
6cc42c63c5
frontend/axi: add wrap burst support
2018-08-29 17:53:26 +02:00
9c729ae7b5
core: replace adr with addr on native interface (closer to AXI and allow some simplifications)
2018-08-29 17:06:03 +02:00
050670829a
core/controller: remove simulation workaround
2018-08-29 16:48:06 +02:00
bc8a9cef7d
README: update
2018-08-29 16:34:53 +02:00
6f7ae8496b
frontend/axi: increase default depth of buffers to improve performance
2018-08-29 16:28:07 +02:00
ed7eef12d4
phy/s7ddrphy: fix preamble/posamble latency when with_odelay (-1 since dqs clk is not shifted)
2018-08-29 14:15:31 +02:00
c37d3af5b5
frontend/bist: only keep random datas (we can generate random addresses with control)
2018-08-28 22:54:23 +02:00
b1e734b2ac
frontend/bist: only use cdc on registers if needed (ie not in sys clock domain)
2018-08-28 18:59:56 +02:00
92c8513598
frontend/axi: add buffer to accept command before converting burst to beats
2018-08-28 14:09:59 +02:00
c15c47497a
test/test_axi: split reads/writes generators
2018-08-28 14:09:12 +02:00
95cb7cdba5
test: rename read/write generators to handlers
2018-08-28 13:40:50 +02:00
Florent Kermarrec
