de12e62ac5
core: use wider DFI address/bank if PHY requires it
2021-03-23 12:41:31 +01:00
7d522cefc3
modules.py: Add MT41J256M8 (Passes mem_test on HW @ sys4x=500MHz, vexriscv, marble board)
2021-03-22 13:55:39 -07:00
f17037fdb2
bench/common: Cleanup, Increase sys_clk measure time to 5s.
2021-03-12 14:29:43 +01:00
3f9759b83b
bench/xcu1525: Update build directories.
2021-03-12 10:59:06 +01:00
df5f555842
bench: Update with recent changes.
2021-03-12 10:25:11 +01:00
e3c2ab0757
phy/usddrphy: Add missing i_RST on DQS's ODELAYE3.
2021-03-04 14:44:07 +01:00
06411b2a72
frontend/dma: Modify CSR interface to be similar to LiteX's DMA (start becomes a enable), also add offset CSR to keep track of current status.
2021-03-04 11:58:33 +01:00
e9d5128811
frontend/dma: Add default CSR values to add_csr. (Allow initializing DMA after reset without software intervention).
2021-03-03 19:42:40 +01:00
25b64c3374
phy/usddrphy: Avoid separate ODELAYE3 by avoiding software reset on DQS's ODELAYE3.
...
The fabric is now maintaining an increment counter for each DQS's ODELAY and software
use it to revert total increments to 0 (equivalent to a reset).
Avoiding the separate ODELAYE3 simplifies design constraints since it was often placed
far from the DRAM pads and thus requiring a LOC constraint to avoid timing violations.
The software has to use the following sdram_write_leveling_rst_delay function:
static void sdram_write_leveling_rst_delay(int module) {
/* Select module */
ddrphy_dly_sel_write(1 << module);
/* Reset DQ delay */
ddrphy_wdly_dq_rst_write(1);
/* Reset DQS delay */
while (ddrphy_wdly_dqs_inc_count_read() != 0) {
ddrphy_wdly_dqs_inc_write(1);
cdelay(100);
}
/* Un-select module */
ddrphy_dly_sel_write(0);
}
2021-03-03 11:29:58 +01:00
541e2f1c57
litedram_gen: Avoid multi-lines on user_port.
2021-03-02 10:54:20 +01:00
d016edf68b
frontend/dma: Drive aw/ar.size when using AXI port.
2021-03-02 10:13:59 +01:00
424b5f956a
litedram_gen: review #234 : rename --module-name to --name add also adapt init file renaming.
2021-03-01 09:25:16 +01:00
aa3ed0bbff
Merge pull request #234 from craigjb/build_name
...
Add module name CLI option
2021-03-01 09:21:04 +01:00
a1c5a10fe2
Add module name CLI option
2021-02-21 13:00:53 -07:00
2d021c842e
test/reference: update.
2021-02-16 18:35:53 +01:00
148d6e1da4
litedram/init: remove SDRAM_PHY_WRITE_LEVELING_REINIT flag on Ultrascale(+) (no longer required).
2021-02-16 16:08:52 +01:00
ba0b22632b
phy/usddrphy: use ic reset (to be sure to follow UG571's reset sequence) and use VAR_LOAD mode on DQS's ODELAYE3.
...
This fixes some reset issues seen on some boards (seen when deployed on large systems with > 100 different boards/controllers),
and avoid having to reload DQS delay from software on DQS reset.
2021-02-16 16:07:13 +01:00
080948d49c
phy/s7ddrphy: add 1866MT/s support.
2021-02-05 11:26:03 +01:00
2c60861929
Merge pull request #232 from antmicro/jboc/init-mr
...
init: make the write leveling MR bit configurable
2021-02-02 09:36:46 +01:00
83b31f4f71
Merge pull request #231 from antmicro/jboc/module-timings
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Allow to pass all module timings in the format (ck, ns)
2021-02-02 09:28:30 +01:00
9d80829e47
Merge pull request #230 from antmicro/jboc/test-init-diff
...
test: improve error messages when comparing files in test_init.py
2021-01-30 21:47:19 +01:00
17db7573fb
Merge pull request #229 from craigjb/port_width
...
Add customizable standalone user port data widths
2021-01-30 21:45:58 +01:00
b3ce582891
test: update ddr3 and ddr4 reference headers to new MR_WLVL defines
2021-01-29 12:49:19 +01:00
f9d39da2e1
init: avoid unnecessary newlines when adding MR_WLVL defines
2021-01-29 12:48:24 +01:00
e7ca72b22f
fix Python init header generation
2021-01-29 12:45:06 +01:00
12d66c119d
phy/model: update DFITimingsChecker to new SDRAMModule timings format
2021-01-29 11:22:33 +01:00
436bfc4fbd
modules: extend parsing of timings to always allow (ck, ns) format
2021-01-29 11:16:16 +01:00
2f5784432d
phys: improve handling of required/optional command pads and make cke/odt optional on all phys.
2021-01-29 09:28:33 +01:00
a1e7d805ec
test: improve error messages when comparing files in test_init.py
2021-01-28 17:44:13 +01:00
bb85ce8f0f
init: make the write leveling MR bit configurable
2021-01-28 16:02:46 +01:00
5a114be7e5
phy/ecp5ddrphy: add clk_polarity parameter to allow inverting clk polarity (for boards with clk_p/n swapped).
2021-01-27 18:36:53 +01:00
562cd3207c
Merge pull request #228 from garytwong/IS43TR16256A
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modules: add IS43TR16256A support.
2021-01-27 08:00:06 +01:00
af9abd6ec9
phy/ecp5ddrphy: remove dm_remapping introduce for VexRiscv-SMP on OrangeCrab: we can now use Wishbone/L2.
2021-01-25 11:54:15 +01:00
5c32dc71c4
Add customizable standalone user port data widths
2021-01-24 21:58:46 -07:00
537e118c6b
modules: add IS43TR16256A support.
2021-01-22 12:30:29 -07:00
ab2423e3dd
litedram_gen: add initial Ultrascale+ support with XCU1525 .yml example.
2021-01-22 12:04:24 +01:00
0127937215
phy/usddrphy: simplify tCK reference by using a specific ODELAYE3 in FIXED mode and keep the PHY in reset by default.
...
Keeping the PHY in reset by default was not possible previously due to the ODELAYE3 configuration
that was lost on reset. Using a specific ODELAYE3 in FIXED mode allow keeping the PHY in reset at
startup.
2021-01-21 18:18:39 +01:00
a91883db23
phy/ecp5ddrphy: add configurable cmd_delay.
...
Allow adding a delay on Clock/Commands. Delay is manual for now but could be
automated in the future if useful (as done on 7-series/Ultrascale(+)).
2021-01-12 18:42:54 +01:00
53e98f75be
phy/ecp5ddrphy: remplace dq_i DELAYF with DELAYG.
2021-01-12 17:32:02 +01:00
919a613733
phy/ecp5ddrphy: use nphases on DFI.
2021-01-12 17:24:10 +01:00
c29c898af4
platforms/targets: switch to LiteX-Boards.
2021-01-04 14:11:32 +01:00
ec1f34f5f9
phy/ecp5/s7/us: allow user to provide cl/cwl instead of default values.
...
One some hardware, forcing cl or/and cwl to non-default values can provide
better results.
2021-01-04 13:22:18 +01:00
d4c5c7cef8
phy/gensdrphy: compute default cl from sys_clk_freq (similar what is already done on other PHYs).
2021-01-04 11:31:13 +01:00
e683b48c4a
common: rename get_cl_cw function to get_default_cl_cwl (and provide retro-compat) and add get_default_cl, get_default_cwl functions.
2021-01-04 11:04:04 +01:00
e9479cca83
phy/gensdrphy: remove unused cmd_latency parameter.
2021-01-04 10:53:47 +01:00
87f95f8442
Merge pull request #226 from mdpye/MT48LC32M8
...
modules: add MT48LC32M8 SDR module
2021-01-03 22:13:19 +01:00
ec37a6353b
modules: add MT48LC32M8 SDR module
2020-12-31 13:10:24 +00:00
103072c68a
test/reference: update.
2020-12-17 18:21:53 +01:00
d8eccebbbc
ci: update RISC-V GCC install.
2020-12-17 17:13:58 +01:00
33f3aa55e5
phy/ecp5ddrphy: add DM remapping capability.
...
Required on OrangeCrab that has LDM/UDM swapped.
2020-12-16 11:49:33 +01:00
Jędrzej Boczar
Vamsi Vytla
Florent Kermarrec
Craig Bishop
Gary Wong
Nathaniel R. Lewis