f1a40cef2f
core: use wider DFI address/bank if PHY requires it
2021-03-25 15:29:32 +01:00
eb1d900c24
lpddr4: S7PHY related fixes, MRR command, runtime configurable WRITE/MASKED-WRITE
2021-03-25 15:29:17 +01:00
052dc19246
lpddr4: improve documentation
2021-03-25 15:21:01 +01:00
1b65e858b3
lpddr4/utils: rework `once` helper function to be more generic
2021-03-25 15:21:01 +01:00
4473335954
lpddr4/commands: replace MPC dict with an enum with docstring
2021-03-25 15:19:16 +01:00
7f19e92c75
ci: add dependencies required for Verilator-based tests
2021-03-25 15:19:16 +01:00
4415a3eaf5
lpddr4: improve simulation and Verilator tests runner
2021-03-25 15:19:16 +01:00
4a5feb9e11
lpddr4/s7phy: improve to use the new DoubleRateLPDDR4PHY
2021-03-25 15:19:16 +01:00
2ab763ac5e
lpddr4: add double-rate PHY, clean up and improve PHY implementation
2021-03-25 15:19:16 +01:00
183f1643aa
lpddr4: add support for MASKED-WRITE
2021-03-25 15:19:16 +01:00
4b78fc99e8
lpddr4/sim: create LPDDR4 simulator and Verilator target
2021-03-25 15:19:16 +01:00
05ed238829
lpddr4: split implementation into multiple files in separate directory
2021-03-25 15:19:16 +01:00
ee9c2b4cf7
lpddr4: implement ZQC through MPC and include it in init sequence
...
We do not yet support ZQC during operation (after init sequence)
as LPDDR4 requires 2-stage ZQC (start+latch) and 1us in between,
which requires modifying Refresher (ZQCExecutor) in LiteDRAM.
2021-03-25 15:19:16 +01:00
055e2dc597
lpddr4: add initial PHY for Series7
2021-03-25 15:19:16 +01:00
4d9106847f
init: add LPDDR4 initialization
2021-03-25 15:19:16 +01:00
788b3f6d02
modules: modules: add LPDDR4 module
2021-03-25 15:19:16 +01:00
6943a1a4a5
lpddr4: initial PHY logic and simulation tests
2021-03-25 15:19:08 +01:00
f0de06091e
core/refresher: use A10=1 for all banks REF
...
This is needed because newer DRAMs like LPDDR4 or DDR5 have
separate commands for per-bank refresh and all banks refresh.
Other DRAM types ignore address for REF commands.
2021-03-24 10:31:06 +01:00
de12e62ac5
core: use wider DFI address/bank if PHY requires it
2021-03-23 12:41:31 +01:00
7d522cefc3
modules.py: Add MT41J256M8 (Passes mem_test on HW @ sys4x=500MHz, vexriscv, marble board)
2021-03-22 13:55:39 -07:00
f17037fdb2
bench/common: Cleanup, Increase sys_clk measure time to 5s.
2021-03-12 14:29:43 +01:00
3f9759b83b
bench/xcu1525: Update build directories.
2021-03-12 10:59:06 +01:00
df5f555842
bench: Update with recent changes.
2021-03-12 10:25:11 +01:00
e3c2ab0757
phy/usddrphy: Add missing i_RST on DQS's ODELAYE3.
2021-03-04 14:44:07 +01:00
06411b2a72
frontend/dma: Modify CSR interface to be similar to LiteX's DMA (start becomes a enable), also add offset CSR to keep track of current status.
2021-03-04 11:58:33 +01:00
e9d5128811
frontend/dma: Add default CSR values to add_csr. (Allow initializing DMA after reset without software intervention).
2021-03-03 19:42:40 +01:00
25b64c3374
phy/usddrphy: Avoid separate ODELAYE3 by avoiding software reset on DQS's ODELAYE3.
...
The fabric is now maintaining an increment counter for each DQS's ODELAY and software
use it to revert total increments to 0 (equivalent to a reset).
Avoiding the separate ODELAYE3 simplifies design constraints since it was often placed
far from the DRAM pads and thus requiring a LOC constraint to avoid timing violations.
The software has to use the following sdram_write_leveling_rst_delay function:
static void sdram_write_leveling_rst_delay(int module) {
/* Select module */
ddrphy_dly_sel_write(1 << module);
/* Reset DQ delay */
ddrphy_wdly_dq_rst_write(1);
/* Reset DQS delay */
while (ddrphy_wdly_dqs_inc_count_read() != 0) {
ddrphy_wdly_dqs_inc_write(1);
cdelay(100);
}
/* Un-select module */
ddrphy_dly_sel_write(0);
}
2021-03-03 11:29:58 +01:00
541e2f1c57
litedram_gen: Avoid multi-lines on user_port.
2021-03-02 10:54:20 +01:00
d016edf68b
frontend/dma: Drive aw/ar.size when using AXI port.
2021-03-02 10:13:59 +01:00
424b5f956a
litedram_gen: review #234 : rename --module-name to --name add also adapt init file renaming.
2021-03-01 09:25:16 +01:00
aa3ed0bbff
Merge pull request #234 from craigjb/build_name
...
Add module name CLI option
2021-03-01 09:21:04 +01:00
a1c5a10fe2
Add module name CLI option
2021-02-21 13:00:53 -07:00
2d021c842e
test/reference: update.
2021-02-16 18:35:53 +01:00
148d6e1da4
litedram/init: remove SDRAM_PHY_WRITE_LEVELING_REINIT flag on Ultrascale(+) (no longer required).
2021-02-16 16:08:52 +01:00
ba0b22632b
phy/usddrphy: use ic reset (to be sure to follow UG571's reset sequence) and use VAR_LOAD mode on DQS's ODELAYE3.
...
This fixes some reset issues seen on some boards (seen when deployed on large systems with > 100 different boards/controllers),
and avoid having to reload DQS delay from software on DQS reset.
2021-02-16 16:07:13 +01:00
080948d49c
phy/s7ddrphy: add 1866MT/s support.
2021-02-05 11:26:03 +01:00
2c60861929
Merge pull request #232 from antmicro/jboc/init-mr
...
init: make the write leveling MR bit configurable
2021-02-02 09:36:46 +01:00
83b31f4f71
Merge pull request #231 from antmicro/jboc/module-timings
...
Allow to pass all module timings in the format (ck, ns)
2021-02-02 09:28:30 +01:00
9d80829e47
Merge pull request #230 from antmicro/jboc/test-init-diff
...
test: improve error messages when comparing files in test_init.py
2021-01-30 21:47:19 +01:00
17db7573fb
Merge pull request #229 from craigjb/port_width
...
Add customizable standalone user port data widths
2021-01-30 21:45:58 +01:00
b3ce582891
test: update ddr3 and ddr4 reference headers to new MR_WLVL defines
2021-01-29 12:49:19 +01:00
f9d39da2e1
init: avoid unnecessary newlines when adding MR_WLVL defines
2021-01-29 12:48:24 +01:00
e7ca72b22f
fix Python init header generation
2021-01-29 12:45:06 +01:00
12d66c119d
phy/model: update DFITimingsChecker to new SDRAMModule timings format
2021-01-29 11:22:33 +01:00
436bfc4fbd
modules: extend parsing of timings to always allow (ck, ns) format
2021-01-29 11:16:16 +01:00
2f5784432d
phys: improve handling of required/optional command pads and make cke/odt optional on all phys.
2021-01-29 09:28:33 +01:00
a1e7d805ec
test: improve error messages when comparing files in test_init.py
2021-01-28 17:44:13 +01:00
bb85ce8f0f
init: make the write leveling MR bit configurable
2021-01-28 16:02:46 +01:00
5a114be7e5
phy/ecp5ddrphy: add clk_polarity parameter to allow inverting clk polarity (for boards with clk_p/n swapped).
2021-01-27 18:36:53 +01:00
562cd3207c
Merge pull request #228 from garytwong/IS43TR16256A
...
modules: add IS43TR16256A support.
2021-01-27 08:00:06 +01:00
Jędrzej Boczar
Vamsi Vytla
Florent Kermarrec
Craig Bishop