To support a simple GMII simulation, skip clock generation and buffer
logic. This allows to operate a GMII interface over sys_clk. Proper
GMII clocking support can still be added in the simulation, this
should work when setting model = False.
It also sets an attribute "model" such that we can avoid adding
Platform constraints in the rest of the ecosystem (such as
litex/litex/soc/integration/soc.py, add_ethernet and add_etherbone).
Signed-off-by: Leon Schuermann <leon@is.currently.online>
Adds support for 64-bit wide XGMII PHYs in LiteEth. A 64-bit wide
XGMII data path is a common method to interconnect multi-gigabit
Ethernet inside FPGAs. This module expects a 64-bit MAC data path,
which is to be added later. It has been tested locally using a
rewritten XGMII module for the LiteX simulator as well as on a KCU116
board.
This work has been inspired by enjoy-digital/liteeth#21 but is
entirely rewritten using Migen FSMs and with respect to
IEEE802.3-2018. Thanks to Florent Kermarrec (@enjoy-digital) and Vamsi
Vytla (@jersey99) for providing the base implementation.
This implementation does not yet support proper 32-bit (DDR) XGMII
PHYs, although support can be easily added by an additional module
which performs the DDR encoding / decoding of the data respectively.
Signed-off-by: Leon Schuermann <leon@is.currently.online>
Since only the reg of the widest engine is needed, the rest can be
removed
reverse_bits is also a bit more readable
The range for the engine data could be removed, but it's more
understandable this way
Per default, the processing should occur with sys_clk and dw, instead of
the phy parameters since it's not that much larger and allows for easier
timing requirements. But on some fpgas saving the few gates could be desirable
On ecp5 `FullMemoryWE` leads to an increase of DP16KD block mem, while
it works better on Intel/Altera devices according to
6c3af746e2.
Simple solution: Make it configurable
Fixes a bug which would fill the TX return channel FIFO whenever the
SRAM Reader FSM is in the IDLE state. Instead, the FIFO should be
filled when the FSM reaches the END state, in which it will remain for
exactly a single clock cycle.
Fixes: 392414eef8 ("mac: Review Timestamping, simplify and...")
Signed-off-by: Leon Schuermann <leon@is.currently.online>
- Simplify names (timestamp_source --> timestamp, tx/tx_timestamp CSR/Layouts --> timestamp, etc...)
- Simplify the logic a bit.
- Use consistent names for FIFO between Writer and Reader (cmd_fifo and stat_fifo).
- Avoid stat_fifo on Reader when Timestamp is disabled.
- Use EventSourceLevel() on Reader only when Timestamp is enabled.
This implements optional packet timestamping based on a hardware
timestamp source for outgoing Ethernet packets, as required by
applications such as IEEE 1588 (Precision Time Protocol).
Florent Kermarrec
Leon Schuermann
David Sawatzke
Anton Blanchard
Jędrzej Boczar