359918c2a2
Comment out template overrides for now.
2019-12-30 19:23:05 +01:00
1f32dcf662
partner: rename orange_crab to orangecrab
2019-12-30 12:07:34 +01:00
8965b01347
partner/orange_crab: cleanup, make it similar to others targets and only keep BaseSoC
2019-12-30 11:54:53 +01:00
e77afaaef0
partner: add OrangeCrab support ( https://github.com/gregdavill/OrangeCrab )
2019-12-30 11:54:45 +01:00
48476be9e2
aller/nereid/tagus: LitePCIeWishboneBridge's shadow_base replace with base_address
2019-12-14 22:10:04 +01:00
7184032555
aller/neired/tagus: fix gateware/software build directory
2019-12-14 11:29:15 +01:00
4334ba9527
partner/aller, nereid, tagus: Remove deprecated param
...
get_csr_header parameter with_shadow_base
removed/deprecated in litex 2a8d8c8f. New default
behavior matches the desired behavior in these targets.
2019-12-14 01:04:28 +00:00
3012cf75fe
partner/aller, nereid, tagus: Use updated csr APIs
...
litex commit 8be5824e258b84df240d34636aaa539124b92c65 simplified the handling
of csr regions and constants.
2019-12-14 01:00:52 +00:00
8fa3f09226
partner/c10prefkit: apply ethernet constraints on nets as done on Xilinx devices.
2019-12-06 15:22:40 +01:00
5193f7155a
partner/aller,nereid & tagus: fix compilation
2019-12-03 09:37:18 +01:00
f7fbfb4639
partner/community/targets: uniformize, improve presentation
2019-12-03 09:33:08 +01:00
1b1370d086
official/targets: uniformize, improve presentation
2019-12-03 09:07:09 +01:00
4e13b7fdab
targets: fomu: move SoCCore import definition
...
The SoCCore definition used to be available under litex.soc.integration,
however it was removed in
626533ce9d
2019-11-25 12:46:21 +08:00
45b847b466
fomu: add documentation to crg
...
This documentation can be fetched using a package such as lxsocdoc.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-11-23 12:55:26 +08:00
5bd8c4d74f
targets/trellisboard: use ECLKBRIDGECS to allow ECLK to reach all DDR banks (fixes Diamond build)
2019-11-01 10:52:56 +01:00
1ae26dd499
targets: use type="io" instead of io_region=True
2019-10-30 16:35:32 +01:00
8878c0a84a
versa_ecp5, trellisboard: add trellis toolchain specific arguments
...
Sync up with Litex commit #49372852d.
2019-10-29 12:32:41 -04:00
5f80633154
targets: increase integrated ROM size if EthernetSoC used
...
Sync up with litex commit #201218b2c.
2019-10-29 12:32:41 -04:00
91083f99a8
ulx3s: simplify SDRAM module selection
2019-10-13 21:15:22 +02:00
6f3b194bd3
Merge pull request #20 from lolsborn/ulx3s-target
...
memory device selection for ulx3s
2019-10-13 20:59:16 +02:00
abf6f7b09a
memory device selection for ulx3s
2019-10-13 09:27:33 -07:00
53d5ed1226
Merge pull request #19 from lolsborn/ulx3s-target
...
add sys clock freq flag, uses same method as current versa code
2019-10-13 10:32:43 +02:00
34507eb431
add sys clock freq flag, uses same method as current versa code
2019-10-13 00:44:07 -07:00
785909ac5f
targets: switch from shadow_base to io_regions
2019-10-09 11:09:59 +02:00
19e2a12266
Merge pull request #18 from xobs/fomu-cpu-updates
...
Fomu cpu updates
2019-09-27 16:55:27 +08:00
48cd1208df
targets: sync with litex targets
2019-09-25 14:09:25 +02:00
0ead12bae8
targets/ulx3s: revert to cl=2
2019-09-25 13:58:45 +02:00
c8e8f254ca
targets: fomu: add USBSoC and default to heap placer
...
The heap placer is important enough that we should just make it the
default.
Also, add a `USBSoC` that includes the required interrupt table, as this
must be specified prior to calling `__init__()`.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-17 17:08:05 +08:00
218bd353c1
targets: fomu: use memory array for sram address
...
Use the memory array to find the address for the sram bank.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-17 17:07:26 +08:00
348677598d
targets: fomu: support building with a cpu
...
Allow the user to specify a CPU.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-17 17:06:23 +08:00
e94c6c8f27
partner/netv2: switch to MVP (K4B2G1646F instead of MT41J128M16)
2019-09-12 09:52:13 +02:00
91feb59f49
Merge branch 'master' of http://github.com/litex-hub/litex-boards
2019-09-11 23:02:44 +02:00
a92ce32f91
targets/netv2: add clk100 (for framebuffer)
2019-09-11 23:02:21 +02:00
91a1520655
add initial Trenz Cyclone 10 LP RefKit support with SDRAM/HyperRAM/Ethernet
2019-09-10 11:32:29 +02:00
c6bb34d78a
partner/targets/nereid: MT8KTF51264 now in LiteDRAM
2019-09-09 08:50:06 +02:00
b4eefa6c33
import: allow importing directly from litex_boards.platforms or litex_boards.targets
2019-09-03 15:30:20 +02:00
ec5540454b
partner: aller/nereid/tagus fix copyright (Rohit Singh as main author), do some cosmetic
2019-09-02 11:43:30 +02:00
cd527f0fcb
Merge branch 'master' into master
2019-09-02 11:29:22 +02:00
d78965ffb2
partner/targets/fomu fix copyright & mode
2019-09-02 11:23:43 +02:00
bdbd2ec1c0
partner: add fomu target
...
This adds the Fomu target back in. The default BaseSoC supports
various USB methods, and will be updated as more become available.
The debug bridge may optionally be added.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-02 14:18:09 +08:00
e704014b36
targets/__init__: comment targets import until we found a way to avoid litedram/liteeth dependecies for targets no using them.
2019-09-01 11:43:21 +02:00
346621b9fc
partner: add platforms and targets for aller, tagus and nereid boards
2019-09-01 03:02:04 -05:00
f661ee0ec9
targets: fix import
2019-08-26 11:00:12 +02:00
ac58d57a83
targets: import platforms from litex_boards.platforms
2019-08-26 09:09:40 +02:00
b84308cb58
list all platforms/targets in platforms.py, targets.py to ease import
2019-08-26 09:07:07 +02:00
2596b20982
partner/targets/fomu: remove for now since only has a CRG (we'll add one later with a real design)
2019-08-07 09:08:11 +02:00
bbf0e770e9
partner/targets/trellisboard: cleanup/update
2019-07-12 19:39:12 +02:00
a792502756
targets: make sure all targets have copyrights & #!/usr/bin/env python3
2019-07-12 19:36:49 +02:00
e470b55d2b
fomu, trellisboard: +x
2019-07-12 19:24:08 +02:00
a88970a67f
move trellis board from community to partner
2019-07-12 19:23:21 +02:00
Tim 'mithro' Ansell
Florent Kermarrec
Greg Davill
Derek Kozel
Sean Cross
Gabriel Somlo
Steven Osborn
Antti Lukats
Rohit Singh