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297 Commits

Author SHA1 Message Date
Florent Kermarrec 333fb362ca Move import Compat directly to litex_boards.__init__.py and simplify. 2021-03-25 16:47:47 +01:00
Florent Kermarrec 062b899e29 platforms/targets: Add mode Vendor prefixes. 2021-03-25 16:19:11 +01:00
Florent Kermarrec 5253a3c43e test/ci: Fix/Update. 2021-03-25 14:21:13 +01:00
Florent Kermarrec 8a3cacae32 boards: Add Vendor prefix to platforms/targets name when useful and when multiple boards from the same vendor. (With Retro-Compat on the imports). 2021-03-25 14:11:17 +01:00
Kaz Kojima cb4e00c3f2 colorlight_i5: Integrate Video Terminal and Video Framebuffer with new VideoECP5HDMIPHY. 2021-03-20 07:56:59 +09:00
Gabriel Somlo 7a1fe7a6bc nexys4ddr: add pmod connectors, and optional sdcard on pmodd 2021-03-19 12:33:11 -04:00
enjoy-digital 6d32c76aa2
Merge pull request #188 from hansfbaier/848-deca-video-bloat 
fix #848: allow ram initialization in bitstream to enable block ram
 2021-03-19 11:11:05 +01:00
Florent Kermarrec ddd46205aa ulx3s: Integrate Video Terminal and Video Framebuffer with new VideoECP5HDMIPHY. 2021-03-18 15:06:35 +01:00
Florent Kermarrec 4330769add minispartan6: Integrate Video Terminal and Video Framebuffer with new VideoS6HDMIPHY. 2021-03-18 14:10:42 +01:00
Hans Baier b7d86df01d fix #848: allow ram initialization in bitstream to enable block ram inference for ROM/RAM with initial value 2021-03-18 08:41:19 +07:00
Hans Baier 8b69ee57a6 arrow_sockit: get video terminal working on VGA 2021-03-16 12:31:41 +07:00
Florent Kermarrec 0e2d9a571e alveo_u280: Fix copyrights (avoid too much cascading on Platforms/Targets) and generate reset on idelay clock domain (similarly to recent change on others Ultrascale+ boards). 2021-03-10 11:23:27 +01:00
enjoy-digital f4ea3fb0d9
Merge pull request #168 from hplp/alveo_u280 
Alveo U280 board
 2021-03-10 11:16:32 +01:00
enjoy-digital 7c6876df42
Merge pull request #186 from gatecat/mipi_pins_x 
crosslink_nx_vip: Remove constraints for hard MIPI pins
 2021-03-10 11:13:49 +01:00
Florent Kermarrec 47faaf20d5 deca: Integrate Video Terminal (untested, resource issue). 2021-03-09 15:02:30 +01:00
gatecat 496cae54ff crosslink_nx_vip: Remove constraint for MIPI pins 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-08 14:26:40 +00:00
gatecat 547157c9ca crosslink_nx_vip: Fix cam_reset IO configuration 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-05 11:26:56 +00:00
gatecat 542001dddf crosslink_nx_vip: Split camera MCLK to its own resource 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-05 11:18:37 +00:00
Florent Kermarrec 51a0bbfa65 platforms/targets: Harmonize VGA pins and use new Video Terminal on all targets with VGA support. 2021-03-03 18:05:24 +01:00
Florent Kermarrec 3af8ec0c8d targets/nexys4ddr: Replace VGA terminal with new LiteX's VideoTerminal. 2021-03-03 17:10:22 +01:00
Florent Kermarrec 7e3b8ab3b5 icebreaker: Add optional DVI Video Terminal with new LiteX's VideoOut core. 
Tested with: ./icebreaker.py --cpu-type=serv --with-video-terminal --build --flash

https://twitter.com/enjoy_digital/status/1365324823447171074
 2021-03-03 16:21:04 +01:00
enjoy-digital aa5c4f9e5a
Merge branch 'master' into arty-numato-sdcard-pmod 2021-02-25 09:37:34 +01:00
Hans Baier 6f558a5d65 Add board support for Terasic/Arrow DECA board 2021-02-25 12:25:43 +07:00
Joel Stanley 2b49082696 platforms/arty: Add numato sd card pmod 
It has a different layout.

Thanks to David for documenting the pinout in this issue:
https://github.com/enjoy-digital/litex/issues/817

 Expansion Pin 	SD 	SPI SD 	Artix 	Arty-A7 	PMOD PIN 	PMOD Index
 2 		DATA_2 	  	D4 	JD1 		1 		0
 4 		CMD 	MOSI 	D3 	JD2 		2 		1
 6 		DATA_0 	MISO 	F4 	JD3 		3 		2
   		CD 	  	F3 	JD4 		4 		3
 1 		DATA_3 	CS_N 	E2 	JD7 		7 		4
 3 		CLK 	CLK 	D2 	JD8 		8 		5
 5 		DATA_1 	  	H2 	JD9 		9 		6
   	  		  	G2 	JD10

Signed-off-by: Joel Stanley <joel@jms.id.au>
 2021-02-24 14:59:50 +10:30
enjoy-digital 5b28c619d5
Merge pull request #178 from yetifrisstlama/vc707_clk 
fix vc707 default_clk_period
 2021-02-23 12:17:45 +01:00
Florent Kermarrec a90c0bc8f9 platforms/sds1104xe: Integrate changes from https://github.com/360nosc0pe/scope. 2021-02-22 13:45:48 +01:00
Michael Betz 09c3bd616b Merge branch 'master' into vc707_clk 2021-02-19 22:49:46 -08:00
Michael Betz c32e790421 vc707: fix default clock frequency 2021-02-19 22:47:18 -08:00
enjoy-digital 1fcd96971d
Merge pull request #172 from hansfbaier/master 
sockit: Add an option to plug in an UART via the GPIO daughter board, make connector pin numbers one-based
 2021-02-16 22:44:52 +01:00
Florent Kermarrec 975150ca68 platforms/sds1104xe: fix ddram IOStandard (SSTL15, thanks @tmbinc) and add INTERNAL_VREF on ddram banks. 2021-02-16 17:32:41 +01:00
Florent Kermarrec 9baa9d5d83 platform/de10nano: fix programmer (thanks @Godtec, see https://github.com/enjoy-digital/litex/pull/811). 2021-02-12 15:23:17 +01:00
Hans Baier 9a94e835c3 sockit: Add an option to plug in an UART via the GPIO daughter board 2021-02-10 14:52:19 +07:00
Michael Betz 7442c2dada vc707.py: clk156 add missing constraint 2021-02-08 19:04:01 -08:00
Florent Kermarrec fef9dd036a platforms/de0nano: directly use JP1 connector for serial pins. 2021-02-08 09:52:26 +01:00
enjoy-digital ea58ef94a7
Merge pull request #170 from hansfbaier/master 
arrow_sockit: add support for MiSTer XS SDRAM modules
 2021-02-04 16:44:58 +01:00
Jan Kowalewski cdff5e3ca3 nexys_video: enable symbiflow toolchain 
Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
 2021-02-03 14:52:54 +01:00
Hans Baier c64e13f687 arrow_sockit: add support for MiSTer XS SDRAM modules 2021-02-03 09:37:03 +07:00
Sergiu Mosanu a1d830566a added ddr4_sdram_c1 constraints 2021-02-01 12:22:41 -05:00
Florent Kermarrec 7c48af9b50 tec0117: get SDRAM working and increase sys_clk_freq to 25MHz. 
./tec0117.py --build --load

Still some FIXMEs but validate use of the embedded SDRAM with LiteDRAM/LiteX:

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2020 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Feb  1 2021 13:09:35
 BIOS CRC passed (5abceb2e)

 Migen git sha1: 40b1092
 LiteX git sha1: f324f953

--=============== SoC ==================--
CPU:		VexRiscv_Lite @ 25MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		24KiB
SRAM:		4KiB
L2:		0KiB
SDRAM:		8192KiB 16-bit @ 25MT/s (CL-2 CWL-2)

--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2MiB)...
  Write: 0x40000000-0x40200000 2MiB
   Read: 0x40000000-0x40200000 2MiB
Memtest OK
Memspeed at 0x40000000 (2MiB)...
  Write speed: 5MiB/s
   Read speed: 6MiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex> mem_list

Available memory regions:
ROM       0x00000000 0x6000
SRAM      0x01000000 0x1000
SPIFLASH  0x80000000 0x1000000
MAIN_RAM  0x40000000 0x800000
CSR       0x82000000 0x10000

litex> mem_test 0x40000000 0x800000

Memtest at 0x40000000 (8MiB)...
  Write: 0x40000000-0x40800000 8MiB
   Read: 0x40000000-0x40800000 8MiB
Memtest OK

litex>
 2021-02-01 13:32:01 +01:00
Florent Kermarrec 6cce07d9db tec0117: add spiflash4x pins, rework flash function to flash both bitstream/bios. 2021-02-01 13:31:44 +01:00
Florent Kermarrec 0831b33285 tec0117: fix copyrights. 2021-02-01 13:31:39 +01:00
Hans Baier 5e4b29c0b5 sockit: Fix cable name, default to jtag_atlantic 2021-02-01 11:48:06 +07:00
enjoy-digital 601c297c8f
Merge pull request #164 from rdolbeau/ztex213 
Support file for the ZTEX USB-FPGA Module 2.13
 2021-01-30 21:43:07 +01:00
Guillaume REMBERT 31df53ef0a Add flash to SPI flash support for board ECPIX5 (needs update to openfpgaloader.py from litex to work) 2021-01-30 13:19:08 +01:00
Romain Dolbeau 027e57b851 Support file for the ZTEX USB-FPGA Module 2.13 2021-01-30 05:19:18 -05:00
Florent Kermarrec abccd12058 tec0117: add initial SDRAM support for the embedded SDRAM of the SIP. 
Still a WIP but able to do the P&R with modifications on LiteX to generate
the IO_PORT constraints but not the IO_LOC for the SDRAM pins.
 2021-01-29 22:28:40 +01:00
Vadzim Dambrouski 345feddce9 ECPIX-5: ddram: Add missing address pin. 
Fixes #161
 2021-01-29 16:03:43 +03:00
Florent Kermarrec 7525b8772f platforms/fpc_iii: avoid dummy pin on ethernet.rst_n. 
rst_n is optional in LiteEth's PHYs.
 2021-01-29 09:33:33 +01:00
Florent Kermarrec 19767e1a2a platforms/fpc_iii: avoid using dummy pin on odt. 
Now possible with 2f5784432d.
 2021-01-29 09:30:54 +01:00
Florent Kermarrec 6c6d8a1393 platforms/fpc_iii: review/cleanup to increase similarities with others platforms and ease maintenance. 2021-01-29 08:41:10 +01:00