33b0400aed
targets: Update LiteXArgumentParser imports.
2022-11-06 21:39:52 +01:00
9960f38d95
targets: replace LiteXSoCArgumentParser by LiteXArgumentParser, remove tasks done LiteXArgumentParser
2022-11-06 11:27:47 +01:00
548a028730
targets: Switch to LiteXModule to simplify/cleanup code.
2022-10-27 21:21:37 +02:00
45494f60e0
targets: Change SoC/Software headers generation behaviour (Now only generated with --build).
...
Re-generating the SoC/Software headers was causing some un-expected behaviours for users not familiar
with the flow. For example doing a --load with a different configuration, was re-generating the Software
headers and messing up things when trying to run software on the SoC.
2022-05-06 15:14:32 +02:00
a611f035d6
targets: Move CRG before SoCCore init (More logical and simplify some specific reset schemes) and switch SoCCore to one line when possible.
...
Moving CRG simplify reset with NaxRiscv debug module and is in fact more logical.
Also do some minor updates/cosmetic changes while touching CRG/SoCCore.
2022-04-21 12:19:45 +02:00
00ff61baa9
targets: Simplify clock domains and remove useless reset_less.
...
rst was not directly assigned/used on reset_less clock domains, so reset_less
property was not really useful. With the changes on stream.CDC, having a rst
(Even fixed at 0) is now mandatory on clock domains involved in the CDC, so this
also fixes targets.
2022-04-01 11:30:38 +02:00
2a206def0f
targets/ecp5/ddr3: Uniformize cd_sys2x (reset_less).
2022-03-22 17:32:35 +01:00
9d452b0d74
targets: Create target_group for target arguments.
2022-03-21 18:37:40 +01:00
cc8da9d341
targets: Simplify imports and switch to LiteXSocArgumentParser.
...
CPU parameters are now selectively exposed to the user:
./digilent_arty.py --cpu-type=vexriscv_smp --help will show VexRiscv-SMP parameters.
./digilent_arty.py --cpu-type=naxriscv --help will show NaxRiscv parameters.
2022-03-21 16:59:40 +01:00
773444a7dd
targets: Switch to get_bios_filename/get_bitstream_filename.
2022-03-17 09:21:05 +01:00
fccb952c4b
target: Remove ident_version=True no longer required.
2022-01-18 17:13:02 +01:00
53dc00eab7
targets/parser: Rely on argparse.ArgumentDefaultsHelpFormatter to provide default in help description.
...
Also do minor adjustments while doing this.
2022-01-05 17:06:40 +01:00
1920db3535
Add with_led_chaser argument to constructor of boards using LedChaser submodule.
2021-07-06 16:39:37 -05:00
1ca8ef97a1
targets/add_sdram: Specific size only when useful (ie for targets with > 1GB of RAM).
2021-03-29 16:03:19 +02:00
ba01776432
targets/add_sdram: Simplify call by removing useless arguments.
...
- main_ram mem_map is now directly used by add_sdram when origin is None.
- max_sdram_size/min_l2_data_width are no longer exposed as targets arguments this can
still be used enforced directly in the few cases it is useful.
2021-03-29 15:28:31 +02:00
47bdf5f759
targets: Use new CSR automatic allocation (self.add_csr will still work but is no longer required).
2021-03-25 10:11:24 +01:00
5995769b46
targets: Switch to soc_core_args/soc_core_argdict (instead of soc_sdram that is now deprecated, but still supported for now).
2021-03-24 17:22:51 +01:00
d256cc8bd6
camlink_4k: disable leds when serial is used (since pin is shared).
2021-01-25 12:19:29 +01:00
d42af3ea19
targets: add --sys-clk-freq support to all targets.
2020-11-12 18:07:28 +01:00
bd4e92ad13
targets: cleanup, uniformize build arguments between targets.
2020-11-12 11:46:00 +01:00
2b17dc1b89
target: add rst signal to CRG to allow full reset of the SoC on reboot command.
2020-11-04 11:13:42 +01:00
b9ac72cf78
targets: simplify clocking on iCE40/ECP5 targets (AsyncResetSynchronizer now integrated in PLL).
2020-09-01 13:38:32 +02:00
1781be166a
general: add SPDX License identifier to header and specify files are part of LiteX-Boards.
2020-08-23 15:00:17 +02:00
869ceadacb
targets: use platform.request_all on LedChaser.
2020-08-06 20:04:03 +02:00
7a48a61605
targets: add indentifier on all targets.
2020-06-30 18:11:04 +02:00
06edf48897
targets: rename gateware-toolchain parameter to toolchain.
2020-06-02 13:45:05 +02:00
eeba64d7b2
targets: use soc.build_name in load/flash bitstream.
2020-05-21 09:12:29 +02:00
d05b10fd76
target/camlink_4k: add missing import.
2020-05-09 12:27:07 +02:00
6f22f082ff
targets: add LedChaser on platforms with user_leds.
...
Default to Chaser mode and similar user interface than GPIOOut.
2020-05-08 22:16:13 +02:00
2d9543b65e
targets: add build/load parameters on all targets.
2020-05-05 15:11:47 +02:00
84468c2a63
targets/CRG: platforms are now automatically constraining the input clocks.
2020-05-05 11:51:57 +02:00
4185a019f5
targets: manual define of the SDRAM PHY is no longer needed.
2020-04-16 11:25:59 +02:00
3b91e96c42
targets/add_constant: avoid specifying value when value is None (=default)
2020-03-26 09:47:22 +01:00
83e6fb29f8
targets: switch to SoCCore/add_sdram instead of SoCSDRAM.
2020-03-21 12:43:39 +01:00
6f517ad1d6
targets/ecp5: make sure all BaseSoC/EthernetSoc default to trellis.
2020-03-05 10:57:59 +01:00
be5ed35871
targets: default to trellis toolchain on all ECP5 targets (now able to build all supported targets).
2020-02-28 09:46:54 +01:00
8211aca2e8
Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
...
We initially wanted to provide different level of support for the platforms/targets, mainly
to avoid too much maintenance and let each contributor update its contributed platforms and
targets, but it's easier to update all platforms/targets all-together when LiteX evolves or
changes (and that's what has been done on litex-boards since the creation of the repository).
So let just simplify things and avoid this differentiation.
2020-02-03 09:36:30 +01:00
Florent Kermarrec
Gwenhael Goavec-Merou
Joey Bushagour