e94e84eb16
sqrl_xcu1525: Add more QSFP IOs.
2024-07-10 18:20:01 +02:00
c7b436a202
sqrl_xcu1525: Add QSFP-0/1 ref clks and rearrange a bit naming.
2024-07-10 17:04:48 +02:00
00df115e86
sqrl_xcu1525: Add QSFP-0/1 IOs.
2024-07-10 16:44:12 +02:00
0ed9e3ac85
Merge pull request #596 from gaoyichuan/vcu118-fmc
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platforms/xilinx_vcu118: add fmc and pmod connector pinouts
2024-07-10 09:17:41 +02:00
5870b078f8
platforms/xilinx_vcu118: add fmc and pmod connector pinouts
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VCU118 board has one FMC HPC, one FMC+ HSPC and two PMOD connectors,
Vivado board files does not contain pinouts for these, so pinouts are
taken from VCU118 Evaluation Board User Guide (UG1224).
Signed-off-by: Yichuan Gao <gaoyichuan000@gmail.com>
2024-07-06 00:16:53 +08:00
15c6f89b1a
#570 : Update CAN support with LiteX https://github.com/enjoy-digital/litex/pull/2007 .
2024-07-05 10:26:28 +02:00
2e120bf8a4
Merge pull request #570 from disdi/master
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Add support for CTUCAN for Arty & Genesys2 board
2024-07-05 09:21:09 +02:00
ac427feb0a
targets/lattice_certuspro_nx_vvml,lattice_certuspro_nx_evn: switch sys_clk to NXPLL
2024-07-03 12:36:28 +02:00
9898672744
siglent_sdr1104xe: Update IP/MAC addresses.
2024-07-02 17:09:23 +02:00
7a157d787b
lattice_certus_prox_nx: Add missing OpenFPGAALoader import.
2024-07-01 15:58:31 +02:00
1c06988d80
platforms,targets/lattice_certuspro_nx_evn,lattice_certuspro_nx_vvml: set sysconfig SPI_MASTER mode by default at platform level
2024-07-01 11:07:25 +02:00
40204ac815
Merge pull request #595 from trabucayre/lattice_certusnxpro
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Lattice certusnxpro
2024-06-28 13:26:47 +02:00
5813df9b44
Merge pull request #591 from VOGL-electronic/efinix_trion_t20_pulse_reset
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targets: efinix_trion_t20_bga256_dev_kit: add pulse for reset
2024-06-28 13:24:29 +02:00
8579af5710
lattice_certuspro_nx_vvml: new board support
2024-06-28 12:47:57 +02:00
f27bbc9645
lattice_certuspro_nx_evn: new board support
2024-06-28 12:47:16 +02:00
bd58227c86
platforms/sqrl_acorn/_litex_acorn_baseboard_mini_io: Add SFP-I2C and Debug IOs.
2024-06-27 14:55:15 +02:00
4f8540d53e
targets/litex_acorn_baseboard_mini: Switch to _litex_acorn_baseboard_mini_io.
2024-06-27 14:23:43 +02:00
91e787b5c3
platforms/sqrl_acorn: Add _litex_acorn_baseboard_mini_io for LiteX Acorn Baseboard Mini specific IOs.
2024-06-27 14:23:17 +02:00
c205bb756b
targets: efinix_trion_t20_bga256_dev_kit: add pulse for reset
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to do a reset on the trion t20 a pulse is needed.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-06-24 09:14:55 +02:00
75ef26b8e5
platforms/machdyne_mozart_mx1.py: adding default_clk_name, default_clk_period (fix CI failure)
2024-06-22 22:43:06 +02:00
f8d41e880d
Merge pull request #593 from machdyne/master
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machdyne: fix typos; add vanille and lakritz
2024-06-22 21:43:02 +02:00
cb43cdf6f9
targets/machdyne_vanille: set uart_name to stub
2024-06-22 12:13:30 +02:00
a1df389c7e
machdyne: switch to LiteXArgumentParser; add mozart ml2+mx1 and vivaldi ml1
2024-06-22 11:26:43 +02:00
5d62eec8a8
README.md: add vanille and lakritz
2024-06-22 09:32:15 +02:00
34e85c5cf6
machdyne: fix typos; add vanille and lakritz
2024-06-22 09:26:42 +02:00
95f5e030e5
Merge pull request #590 from trabucayre/zynq_csr_master_bus
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ZynqXXX boards: remove CSR definition and GP0 connection to CPU
2024-06-19 08:48:33 +02:00
dad6b2b9b6
efinix_trion_t20_bga256_dev_kit: Cleanup/Review platform/target.
2024-06-19 08:23:54 +02:00
8eaa4d637e
Merge pull request #589 from VOGL-electronic/sdram_efinix_trion_t20
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efinix_trion_t20: add sdram
2024-06-19 08:18:19 +02:00
70fb3de96c
targets: All boards based on Zynq7000: remove csr definition and GP0 connection to the SoC: now handled by zynq700 core CPU
2024-06-19 07:59:24 +02:00
efd6c8b0aa
targets/alinx_axu2cga,xilinx_zcu216,xilinx_kv260: remove csr definition and GP0 connection to the SoC: now handled by znqmp core CPU
2024-06-19 07:54:50 +02:00
07881259a5
litex_acorn_baseboard_mini: Assert cleanups.
2024-06-18 17:41:01 +02:00
6857418deb
litex_acorn_baseboard_mini: Allow simultaneous pcie and ethernet.
2024-06-18 13:56:08 +02:00
805a520b5a
litex_acorn_baseboard_mini: Fix and test PCIe Gen2 X1 with it.
2024-06-18 09:14:08 +02:00
27b99d4169
targets/lambdaconcept_ecpix5.py: allows configuring eth_ip/remote_ip/dynamic
2024-06-14 15:58:25 +02:00
635e932084
targets/lambdaconcept_ecpix5.py: added argument to select version (r02 by default)
2024-06-14 15:57:11 +02:00
6e6246d718
platforms/lambdaconcept_ecpix5.py: create_programmer: added option to select between r03 version (FT4232) and provious (FT2232)
2024-06-14 15:46:36 +02:00
1b22061e93
litex_acorn_baseboard_mini: Add PCIe support (Not yet buildable with Ethernet or SATA due to GTPE2_COMMON sharing).
2024-06-13 17:46:16 +02:00
eebe983914
platforms/sqrl_acorn: Add PCIe X1 pins when mounted in baseboard.
2024-06-13 17:23:26 +02:00
2cd89cdd16
efinix_trion_t20: add sdram
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add sdram of the efinix trion t20 bga256 dev kit.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-06-13 12:16:09 +02:00
ed6ff8f4fe
targets: Switch to LiteX byte size definitions.
2024-06-13 10:04:19 +02:00
a8d31510a4
README.md: Bump year.
2024-06-11 18:58:16 +02:00
ffca906b34
README.md: Add hseda_xc7a35t.
2024-06-11 18:51:48 +02:00
1013a53240
Merge pull request #587 from akioolin/master
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Add HSEDA XC7A35T board support
2024-06-11 18:50:06 +02:00
2fe52995d6
Merge pull request #588 from Joshinken/patch-1
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Update README.md
2024-06-11 18:49:22 +02:00
0e6339847a
version: Bump to 2024.04.
2024-06-05 22:11:47 +02:00
8bb3caee5f
targets/quicklogic_quickfeather: updated qlal4s3b_cell_macro Clock and Reset signals (similar fix to #1797 )
2024-05-30 08:37:14 +02:00
61d81951b2
Update README.md
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fixed typo
2024-05-28 11:05:12 +02:00
3c181106b8
Add HSEDA XC7A35T board support
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Add HSEDA XC7A35T board support
2024-05-21 21:00:27 +08:00
b8d2b513a3
platforms/xilinx_zcu102.py: added PMOD0/1 (j55/j87)
2024-05-21 11:24:22 +02:00
6a7c908ca5
Merge pull request #586 from litex-hub/xilinx_zcu106_fmc
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platforms/xilinx_zcu106.py: added connectors and FMC HPC0/1
2024-05-17 12:51:59 +02:00
Florent Kermarrec
Yichuan Gao
Gwenhael Goavec-Merou
Fin Maaß
inc
Joshinken
Akio