0b028d3956
soc/cores/hyperbus: Add comment to allow switching to SDRTristate.
2024-08-20 22:05:38 +02:00
60f83b71fa
soc/cores/hyperbus: Avoid dq_oe condition to generate dq_o (was only useful for sim but now avoided).
2024-08-20 21:54:15 +02:00
298a004f08
Merge pull request #2045 from enjoy-digital/hyperbus_io_regs
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Improve HyperRAM core to allow IO Reg inference.
2024-08-20 19:47:01 +02:00
3a37d3ba98
software/libbase/hyperram: Add missing #ifdef.
2024-08-20 17:11:02 +02:00
eb29b40e07
soc/cores/hyperbus: Simplify CS and make it synchronous to allow IO Reg.
2024-08-20 16:19:15 +02:00
1998c74549
soc/cores/hyperbus: Make DQ/RWDS input sync explicit to allow IO Reg.
2024-08-20 15:44:53 +02:00
8b86b16077
soc/cores/hyperbus: Make Rst synchronous to allow IO Reg (even if low speed).
2024-08-20 15:26:26 +02:00
76cf004913
test/test_hyperbus: Update.
2024-08-20 15:17:36 +02:00
b0026937c1
soc/software/libbase: Move HyperRAM init code to libbase/hyperram.c.
2024-08-20 14:58:51 +02:00
a30651e44e
soc/cores/hyperbus: Avoid waiting for clk_phase in IDLE state to reduce latency.
2024-08-20 14:44:33 +02:00
b7605bc633
Merge pull request #2044 from VOGL-electronic/json2dts_zephyr_omit_disabled_handler
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json2dts_zephyr: omit disable handler
2024-08-20 14:29:35 +02:00
bfe000150c
soc/cores/hyperbus: Rework Clk generation to allow having using an IO Reg.
2024-08-20 14:25:23 +02:00
7b413352c2
soc/cores/hyperbus: Directly specify default sys_clk_freq in __init__.
2024-08-20 12:04:23 +02:00
8f5c2dfbca
soc/cores/hyperbus: Fix build with SDRTristate (to prepare tests with it).
2024-08-20 12:03:40 +02:00
3a53a92bb2
soc/cores/hyperbus: Simplify/Rework Data Shift-Out Register.
2024-08-20 11:38:33 +02:00
9c1958d692
soc/cores/hyperbus: Simplify/Rework Data Shift-In Register.
2024-08-20 11:26:58 +02:00
c1403db407
json2dts_zephyr: omit disable handler
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omit disable handler for the sdcard peripherals,
as they still don't have a driver in zephyr and are not in the board dts.
This way the build in zephyr will not fail.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-08-20 11:23:21 +02:00
db86ec08b8
soc/cores/hyperbus: Better split parameters/signals and use intermediate dq_o/oe/i and rwds_o/oe/i signals.
2024-08-20 11:12:17 +02:00
1f71f3d68b
soc/cores/hyperbus: Cleanup CSn/Clk generation and add comments.
2024-08-20 10:40:24 +02:00
a960dc33bc
soc/cores/hyperbus: Minor cleanup changes.
2024-08-20 10:26:34 +02:00
b95b66b554
soc/cores/hyperbus: Switch to Tristate instead of TSTriple and prepare for SDRTristate (not enabled for now).
2024-08-20 10:10:53 +02:00
c5416f1680
fixes for apicula support
2024-08-19 19:54:26 +02:00
afc66fd5cf
cores/picorv32: Fix idbus.sel for reads.
2024-08-19 13:34:50 +02:00
bccd1e9c54
CHANGES.md: Update.
2024-08-19 10:37:13 +02:00
6623a5b691
Merge pull request #2028 from VOGL-electronic/spi_ram_add
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soc: add add_spi_ram function
2024-08-16 19:08:48 +02:00
26e7eef3ce
Merge pull request #2042 from pepijndevos/apicula
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Gowin: add dual use gpio options
2024-08-16 18:58:04 +02:00
039be2a248
add dual use gpio options
2024-08-16 15:56:24 +02:00
cbb1adfa7b
Merge pull request #2036 from Mai-Lapyst/gowin-add-apicula
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Adds apicula toolchain to gowin platform
2024-08-15 08:54:40 +02:00
dc3f2d6421
Add missing license header to apicula.py
2024-08-15 01:54:31 +02:00
623536cd6a
Remove empty build_timing_constraints override in GowinApiculaToolchain
2024-08-15 01:52:22 +02:00
e0968b3574
Adds apicula toolchain to gowin platform
2024-08-12 06:55:11 +02:00
b279fc9fb3
Merge pull request #2035 from Mai-Lapyst/fix_empty_initpy
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Fix litex.build.gowin's __init__.py; closes #2034
2024-08-11 10:06:09 +02:00
3d0fe4ebca
Fix litex.build.gowin's __init__.py; closes #2034
2024-08-11 05:44:14 +02:00
6309f30e0b
Merge pull request #2030 from trabucayre/gowin_build_gw5a_primitives
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build/gowin/common.py: re-add tristate impl and SDRxxx for GW5A/Arora family (required for SDRAM use)
2024-08-07 09:23:21 +02:00
cb6e28aaa2
Merge remote-tracking branch 'origin/master' into vexiiriscv
2024-08-05 09:07:39 +02:00
3cd820974a
build/gowin/common.py: re-add tristate impl and SDRxxx for GW5A/Arora family (required for SDRAM use)
2024-08-04 09:39:46 +02:00
cd457c9809
soc: add l2 cache to spi_ram
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Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-08-01 15:51:45 +02:00
e29dc39377
openocd/jtagspi: Allow users to specify additional init commands
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This change makes it possible to e.g. use flahs chips that would not be correctly detected by OpenOCD.
All that has to be done is to add `init_commands=["jtagspi set 0 \"name\" {size} {pagesize} {read_cmd} 0 {pprg_cmd} {mass_erase_cmd} {sector_size} {sector_erase_cmd}"]`.
Signed-off-by: Matthias Breithaupt <m.breithaupt@vogl-electronic.com>
2024-08-01 15:51:45 +02:00
41b346d141
bios: mem_read: reduce number of reads on mapped registers (only supports 32-bit aligned addresses)
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Instead of reading each individual byte, causing multiple 4-byte requests to each address, this
change results in a single read for each address.
Signed-off-by: Matthias Breithaupt <m.breithaupt@vogl-electronic.com>
2024-08-01 15:51:45 +02:00
03a0a6fd9b
soc: add add_spi_ram function
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Signed-off-by: Matthias Breithaupt <m.breithaupt@vogl-electronic.com>
2024-08-01 15:51:45 +02:00
f855417afc
README.md: Be more positive and shorter in moral precisions :).
2024-07-31 14:55:10 +02:00
74127d51c5
Merge pull request #2024 from trabucayre/altera_agilex5_sdrtristate_special
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build/altera/common.py: implement SDRTristate for Agilex5 family
2024-07-30 19:22:25 +02:00
1f6673c6eb
build/altera/common.py: implement SDRTristate for Agilex5 family
2024-07-30 16:36:05 +02:00
3041150773
Merge pull request #2021 from trabucayre/altera_agilex5_ddr_special
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build/altera/common,platform: added ddrinput/ddrout primitives
2024-07-26 18:26:19 +02:00
ba8830e6cd
global: Remove @trabucayre's tracers :)
2024-07-26 12:57:01 +02:00
5c5bc82f22
interconnect/packet/PacketFIFO: Fix payload_fifo.sink.valid.
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Needs to be filtered on param_fifo.sink.ready and not payload_fifo.sink.ready.
2024-07-26 11:52:17 +02:00
dc04949d78
build/altera/common,platform: added ddrinput/ddrout primitives
2024-07-25 14:11:06 +02:00
c51d22074f
soc/integration/soc/add_uart: Allow directly passing uart_pads.
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Useful for test purpose when testing multiple UART peripherals without having to expose them on IOs.
2024-07-22 16:23:22 +02:00
b8cb6da2b9
soc/cores/clock/lattice_nx.py: added clk contraints for OSCA output
2024-07-22 15:11:40 +02:00
ecd0f0e548
cores/ram/lattice_nx: Revert #1906 since not working with RAM combining multiple SP512K.
2024-07-22 14:24:34 +02:00
Florent Kermarrec
Fin Maaß
Pepijn de Vos
Gwenhael Goavec-Merou
Gwenhael Goavec-Merou
Mai-Lapyst
Mai-Lapyst
Dolu1990
Matthias Breithaupt