Commit Graph

9525 Commits

Author SHA1 Message Date
Dolu1990 786c929f08 cores/cpu/vexriscv_smp: fix PLIC_EXT_IRQ_BASE 2024-05-14 14:24:37 +02:00
enjoy-digital 8a83585b85
Merge pull request #1953 from enjoy-digital/export_csr_c_rework
Simplify/Cleanup C exports and disable Fields accessors generation by default.
2024-05-14 12:54:48 +02:00
Florent Kermarrec 8eaa53ae9a test/test_cpu: Disable cv32e40p test (need to update/wait for pythondata to be updated). 2024-05-14 12:53:09 +02:00
enjoy-digital c810b89464
Merge pull request #1951 from nuntipat/update-cv32e40p
Update CV32E40P to be based on the OpenHW Group's repo
2024-05-14 12:11:50 +02:00
enjoy-digital 9b6e231a1a
Merge pull request #1952 from nuntipat/fix-csr-def-cv32e41p
Fix CSR register definition for the CV32E41P core
2024-05-14 12:08:42 +02:00
Florent Kermarrec 46911d5078 soc/integration/builder: Disable fields_access_functions generation by default since not widely used (at least not in LiteX "official" projects). 2024-05-14 11:59:13 +02:00
Florent Kermarrec 2574cc1ddc integration/export: Fix read_function refactoring. 2024-05-14 11:55:34 +02:00
Florent Kermarrec 29bb397bb6 soc/integration/export: Add parameter to enable/disable fields access function generation.
Fields access function have been contributed and probably used by a few project but not really
by LiteX projects or cores itselves.

This generates complex code and compilation warnings, so it can be useful to disable them by default (but still allow used to enable them).
2024-05-14 11:22:46 +02:00
Florent Kermarrec 9f4bd5cec8 integration/export: Split get_csr_header in simpler functions. 2024-05-14 11:00:41 +02:00
Florent Kermarrec c42cc350c6 integration/export: Split _get_rw_functions_c in simpler functions. 2024-05-14 10:47:38 +02:00
Florent Kermarrec 3506a5e82d cores/cpu/vexriscv_smp: Prepare IRQ support based on Rocket IRQ support (not yet working). 2024-05-14 10:04:13 +02:00
Florent Kermarrec 49897ee018 software/libbase/isr.c: Cleanup plic_init/isr and move PLIC_EXT_IRQ_BASE to cores/cpu/../irq.h since specific to each CPU. 2024-05-14 10:02:56 +02:00
Nuntipat Narkthong b0acf6136e Fix CSR register definition for the CV32E41P core 2024-05-13 20:03:16 -04:00
Nuntipat Narkthong 41564cc47b Update CV32E40P to be based on the OpenHW Group's repo 2024-05-13 19:59:42 -04:00
Florent Kermarrec 2613ae606a interconnect/packet/Status: Simplify logic. 2024-05-13 17:52:24 +02:00
Florent Kermarrec 8b175c2575 CHANGES: Update. 2024-05-13 16:33:11 +02:00
enjoy-digital 0d3a8220dd
Merge pull request #1948 from Liamolucko/riscv-triples
Add missing 32-bit variants of RISC-V target triples
2024-05-07 15:15:09 +02:00
enjoy-digital b61e8b5d42
Merge pull request #1945 from Nicolas-Gaudin/master
Support isr for cv32e41p core
2024-05-07 15:13:44 +02:00
enjoy-digital e4cfe87109
Merge pull request #1946 from nrndda/AXILite_LitexXModule_revert
Revert LitexModule for AXILiteSRAM as well.
2024-05-07 15:10:55 +02:00
Florent Kermarrec 86a43c9ff7 integration/export: Fix get_csr_header/base_define when with_csr_base_define is set to False. 2024-05-06 14:59:17 +02:00
Liam Murphy e07c4fdb2a
Add missing 32-bit variants of RISC-V target triples
I had to waste another 10-15 minutes building a `riscv64-none-elf` GCC
instead after LiteX didn't like my `riscv32-none-elf` one, so I thought
I'd quickly add it. (I was using that target triple because it's what
Nix's `pkgsCross.riscv32-embedded` package set uses).

I also added 32-bit variants of the rest of the target triples which
didn't have them.
2024-05-04 17:41:32 +10:00
Dmitry Derevyanko 26f5e8a149 Revert LitexModule for AXILiteSRAM as well. Follows revert d021564fca for wishbobe. 2024-05-03 00:51:01 +03:00
Nicolas Gaudin bd0adb5be7
Support isr for cv32e41p core 2024-04-30 14:07:07 +02:00
enjoy-digital 76a704377f
Merge pull request #1941 from motec-research/vexriscv_debug_halted
cpu/vexriscv: expose o_halted
2024-04-26 13:43:40 +02:00
Dolu1990 7aae2bf897
Merge pull request #1940 from enjoy-digital/Dolu1990-patch-1
cpu/naxriscv update mBus to preserve memory accesses offset
2024-04-26 11:21:18 +02:00
Florent Kermarrec fd477703db soc/integration/export: Revert #1938 (needs to be reviewed/discussed). 2024-04-26 10:59:02 +02:00
AndrewD bd4ca4371d
Merge pull request #1938 from motec-research/guard_access_function
soc/export: add guard for access_functions
2024-04-26 12:06:49 +10:00
Andrew Dennison 3a008b4988 cpu/vexriscv: expose o_halted 2024-04-26 11:17:41 +10:00
Dolu1990 ea33e37b1a
cpu/naxriscv update mBus to preserve memory accesses offset
See #1922
2024-04-25 16:06:34 +02:00
enjoy-digital b6bfe42b6b
Merge pull request #1937 from motec-research/litex_term_deprecation_warning
tools/litex_term: fix DeprecationWarning
2024-04-25 11:38:09 +02:00
enjoy-digital ac1166946c
Merge pull request #1936 from motec-research/fix_recursive_exception
get_data_mod(): fix recursive exception reporting
2024-04-25 11:37:41 +02:00
Gwenhael Goavec-Merou 546f4d93ff
Merge pull request #1939 from hansfbaier/master
yosys+nextpnr: fix error message
2024-04-25 07:03:44 +02:00
Hans Baier d73190ac29 yosys+nextpnr: fix error message 2024-04-25 06:23:22 +07:00
Andrew Dennison 7481b1e161 soc/export: add guard for access_functions
Disable access functions with -DLITEX_ACCESS_FUNCTIONS=0 when compiling.
Useful when using litex generated headers in an environment where
the access functions generate warnings and are not used.
2024-04-22 12:16:48 +10:00
Andrew Dennison 19db78da15 get_data_mod(): fix recursive exception reporting 2024-04-22 12:09:45 +10:00
Andrew Dennison 60d9a635ce tools/litex_term: fix DeprecationWarning
litex/litex/tools/litex_term.py:557: DeprecationWarning: setDaemon() is deprecated, set the daemon attribute instead
  self.reader_thread.setDaemon(True)
litex/litex/tools/litex_term.py:586: DeprecationWarning: setDaemon() is deprecated, set the daemon attribute instead
  self.writer_thread.setDaemon(True)
2024-04-22 11:43:17 +10:00
Florent Kermarrec d324c0e150 test/test_cpu: Disable Microwatt that seems to be broken. 2024-04-20 08:51:10 +02:00
enjoy-digital e4dc68206d
Merge pull request #1932 from trabucayre/fix_openxc7
build/xilinx/yosys_nextpnr.py: fix device name for xc7a35ticsg324-1L & xc7a200t-sbg484-1 (as done for f4pga)
2024-04-19 13:43:31 +02:00
Gwenhael Goavec-Merou 7f7e44646d build/xilinx/yosys_nextpnr.py: fix device name for xc7a35ticsg324-1L & xc7a200t-sbg484-1 (as done for f4pga) 2024-04-19 06:57:01 +02:00
Florent Kermarrec d6eeb20505 tools/litex_term: Minor cosmetic changes. 2024-04-18 15:09:24 +02:00
Gwenhael Goavec-Merou 22f4637570 Revert "Uart tx irq handling fix " (issue #554)
This reverts commit 6885770e47.
2024-04-16 14:01:38 +02:00
Florent Kermarrec 3978af9c39 test/test_hyperbus: Update. 2024-04-16 11:12:30 +02:00
Florent Kermarrec a44b7944ca CHANGES: Update. 2024-04-16 10:51:19 +02:00
Florent Kermarrec fd6f913525 cores/hyperbus: Switch default latency_mode to variable. 2024-04-16 10:20:18 +02:00
Florent Kermarrec 62b9c64212 cores/hyperbus: Add status register to report configured latency_mode to software and allow corresponding configuration. 2024-04-16 10:18:53 +02:00
enjoy-digital 576ab24b6c
Merge pull request #1926 from enjoy-digital/hyperbus_variable_latency
HyperRAM: Add variable latency and configuration support.
2024-04-15 17:39:04 +02:00
enjoy-digital e3d1391487
Merge pull request #1925 from chmousset/fix_efinix_t8q144
[fix] T8Q144 PLL input instance reference
2024-04-15 17:38:37 +02:00
Florent Kermarrec ebabe82c70 software/bios/main: Rewrite HyperRAM init/config. 2024-04-15 16:03:55 +02:00
Florent Kermarrec 67586e8a24 cores/hyperbus: Update docstring. 2024-04-15 15:05:58 +02:00
Florent Kermarrec d25fd85f55 cores/hyperbus: More cleanups. 2024-04-15 14:56:08 +02:00