Commit Graph

9525 Commits

Author SHA1 Message Date
Florent Kermarrec 129446dea2 test/test_wishbone: Run all Remapper tests in byte and word modes and simplify. 2024-02-21 11:20:01 +01:00
Florent Kermarrec c1dad9516a interconnect/wishbone/Remapper: Shift origin when in word mode, fixes unit-test. 2024-02-21 11:06:15 +01:00
Florent Kermarrec 6213fd2151 test/test_wishbone: Add Remapper unit-test for word addressing mode. 2024-02-21 11:05:35 +01:00
Florent Kermarrec c0517cd1cf interconnect/axi: Use same default parameters than wishbone.Remapper. 2024-02-20 16:58:37 +01:00
Florent Kermarrec d1e73889f9 test/test_wishbone: Add wishbone.Remapper basic tests. 2024-02-20 16:51:32 +01:00
Florent Kermarrec ef256c9cc2 interconnect/wishbone: Enhance Remapper to also integrate RegionsRemapper functionnality and apply operation sequentially. 2024-02-20 16:50:56 +01:00
Florent Kermarrec d78dbd6935 soc/add_spi_flash: Revert PHY_FREQUENCY definition and use in BIOS. 2024-02-20 14:23:54 +01:00
Gwenhael Goavec-Merou 03340bcf12 soc/software/liblitespi/spiflash: replace SPIFLASH_PHY_FREQUENCY by CONFIG_CLOCK_FREQUENCY (removed by commit e498a56698) 2024-02-19 06:34:26 +01:00
enjoy-digital 677443cef7
Merge pull request #1890 from rtucker85/fix_csr_merge
Fixes for errors when attempting import of Sub-SoCs .json
2024-02-16 18:27:39 +01:00
Richard Tucker 6c8633b9a3 soc/integration/builder: add_json: fix order of parameters
For consistancy only. This now matches load_csr_json.

Link: https://git.motec.com.au/id/Ibe2889fafc6ef48a6f217f84246de11a9555811d
2024-02-16 16:59:14 +11:00
Richard Tucker d4c1c97cf9 soc/integration/export: fix incorrect element in get_linker_regions 2024-02-16 15:38:48 +11:00
Florent Kermarrec cfbe3b028a interconnect/wishbone/RegionsRemapper: Add default values for src_regions/dst_regions. 2024-02-13 19:13:00 +01:00
Florent Kermarrec 595118fd5d interconnect/wishbone/RegionsRemapper: Connect adr by default when no remapping. 2024-02-13 18:31:05 +01:00
Florent Kermarrec 5ee746f178 interconnect/wishbone: Add initial RegionsRemapper to allow remapping source regions to destination regions. 2024-02-13 18:25:46 +01:00
Florent Kermarrec 19db80ec9b interconnect/Remapper: Add docstring description. 2024-02-13 17:44:02 +01:00
Florent Kermarrec fe0363da25 CHANGES.md: Update. 2024-02-13 16:04:13 +01:00
Florent Kermarrec bd7921cda8 soc/add_master: Add region support to allow remapping.
Allow connecting a master to a specific region of the SoC and limiting access to it.
2024-02-13 15:59:42 +01:00
Florent Kermarrec 36767c66b4 soc/SoCRegion: Ensure fixed indentation in __str__. 2024-02-13 14:52:29 +01:00
enjoy-digital 46a2e6fe78
Merge pull request #1887 from Dolu1990/jtag
tools/litex_sim support for remote_bitbang (openocd)
2024-02-13 14:29:11 +01:00
enjoy-digital 89bf0fb0cf
Merge pull request #1888 from Dolu1990/reset_vector
core/vexriscv_smp add reset vector support
2024-02-13 11:43:40 +01:00
Dolu1990 795fa1e1fc core/vexriscv_smp add reset vector support 2024-02-13 11:22:05 +01:00
Dolu1990 0a315cda2d Merge branch 'master' into jtag
# Conflicts:
#	litex/soc/cores/cpu/vexriscv_smp/core.py
2024-02-13 10:41:26 +01:00
Dolu1990 fe37dcf6dd tools/litex_sim now support remote_bitbang (openocd)
soc/cores/vexriscv_smp add jtag tap support
2024-02-13 10:35:53 +01:00
Florent Kermarrec f36e7d379a CHANGES.md: Update. 2024-02-12 17:21:42 +01:00
Florent Kermarrec 244bc43886 soc/integration/builder: Add add_json method to allow adding exported .json from Sub-SoCs.
Ex: builder.add_json("icebreaker_soc.json", 0x30000000, "icebreaker_soc") to import/merge
a SoC's json file from a Sub-SoC in Main-SoC.
2024-02-12 17:19:04 +01:00
Florent Kermarrec 38ff48a543 soc/integration/export: Add load_csr_json function to load/import .json exports.
Useful to merge SoC/Sub-SoCs Constants/CSRs/Memory Regions.
2024-02-12 17:16:54 +01:00
Florent Kermarrec 1b32d8a341 soc/add_etherbone: Revert sys_clk domain renaming when ethmac is disabled. 2024-02-09 15:10:47 +01:00
Florent Kermarrec afcf78f643 soc/add_etherbone: Rename ethmac parameters with ethmac suffix since related to ethmac. 2024-02-07 19:21:38 +01:00
enjoy-digital 0ed44a2c04
Merge pull request #1886 from trabucayre/etherbone_hybrid_ip_mac
Etherbone hybrid ip mac
2024-02-07 14:15:42 +01:00
Gwenhael Goavec-Merou 7f211048ac soc/integration/soc/add_etherbone: adding ethernet mac address, local/remote ip as parameters, sanity check when hybrid mode and adding ip/mac constants 2024-02-07 12:49:03 +01:00
Gwenhael Goavec-Merou 177df0b57e soc/integration/soc: move add_ip_constant to helpers with a renaming to add_ip_address_constants, adding function to add MACADDRx constant 2024-02-07 12:44:59 +01:00
Gwenhael Goavec-Merou e866892798 soc/software/bios/boot: allow to override macaddr by using constant MACADDRx 2024-02-07 11:16:12 +01:00
Gwenhael Goavec-Merou 13c57e8304 soc/integration/soc: add_etherbone/ClockDomainRenamer: keep sys connected to sys instead of eth rx 2024-02-07 07:21:35 +01:00
Florent Kermarrec 57bc0369c7 integration/soc/SocCSRHandler: Make supported_address_width/paging values explicit. 2024-02-05 12:57:06 +01:00
enjoy-digital 88e530d0e8
Merge pull request #1885 from smunaut/csr-paging-0x400
soc/integration: Allow 0x400 CSR paging
2024-02-05 12:44:51 +01:00
enjoy-digital cd1088dbe9
Merge pull request #1884 from motec-research/efinix_spi_width
Efinix: suport spi width for passive loading
2024-02-05 12:43:30 +01:00
Sylvain Munaut 3127e504d3 soc/integration: Allow 0x400 CSR paging
It's a convenient way to get more CSR locations without changing
the whole address space layout (i.e. more space for CSR).

It still leaves 256 full 32b registers in each location which
I've never encountered a device even coming close to this, so
it should be fairly safe to do.

This doesn't change the default, just allow the user to select it.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2024-02-05 11:45:34 +01:00
Andrew Dennison f81c940e7b litex/build/efinix: add binary output
This is the file required for passive SPI loading.
2024-02-05 11:00:39 +11:00
Andrew Dennison d9f006e123 litex/build/efinix: add spi_width
Doesn't seem needed for Trion but probably essential for Titanium?
2024-02-05 11:00:39 +11:00
Florent Kermarrec a59b67e4ee soc: Avoid .upper() on add_config/constant since already done in methods. 2024-02-01 08:44:52 +01:00
Florent Kermarrec e498a56698 soc/add_spi_flash: Minor integration cleanup and remove PHY_FREQUENCY constants that is no longer used. 2024-02-01 08:42:11 +01:00
Florent Kermarrec e44631294a CHANGES.md: Update. 2024-02-01 08:34:17 +01:00
enjoy-digital be23467cb1
Merge pull request #1881 from motec-research/spiflash_fixes
Spiflash fixes for issues exposed by sys_clk = 200MHz and L2 cache
2024-02-01 08:33:36 +01:00
Andrew Dennison fc85fdd178 build/openfpgaloader: support args with '-'
many openfpgaloader args have a name with '-' as per normal convention.

This kwarg now works: file_type="raw"
2024-02-01 15:53:51 +11:00
Andrew Dennison afe7b93995 software/liblitespi/spiflash: fix warnings 2024-02-01 14:37:22 +11:00
Andrew Dennison de594e44c9 software/bios/cmds: fix crc command with L2 cache
Same CRC was always reported if the memory region was in the cache...
Noticed when manually testing spiflash divisor.
2024-02-01 14:37:22 +11:00
Andrew Dennison 3a890a077b software/liblitespi/spiflash: fix clk_freq tuning with L2 cache
Correct CRC was always calculated, regardless of divisor, as the
test flash block was in the L2 cache. This resulted in the minimum
divisor being used and incorrect flash reads with 200MHz sys_clock.
2024-02-01 14:37:22 +11:00
Andrew Dennison e0416639f7 software/liblitespi/spiflash: fix reported flash clk 2024-02-01 14:37:22 +11:00
Andrew Dennison 51c3cb3552 soc/add_spi_flash: default clk_freq to 20MHz
This is safer than defaulting to sys_clock / 2 if sys_clock > 100MHz
clk_freq tuning will result in a faster clock if supported by hardware.
2024-02-01 14:37:22 +11:00
Andrew Dennison 1dddfa6841 soc/add_spi_flash: fix default divisor and PHY_CLOCK calculation
Ensure default_divisor is set to desired default - 1 as required by LiteSPIClkGen
Calculate actual PHY_CLK based on default_divisor
2024-02-01 14:37:22 +11:00