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177 Commits

Author SHA1 Message Date
enjoy-digital ff271b0b5f
Merge pull request #1816 from motec-research/test_csr_status_issue 
test_csr: test cases to demonstrate a CSRStatus() issue
 2023-10-27 12:52:25 +02:00
Florent Kermarrec 002aad7a43 soc/test: Make data_width/address_width/addressing explicit on Wishbone.Interface calls. 2023-10-27 10:55:13 +02:00
Andrew Dennison 203726bc03 test_csr: test cases for issue 
'status' reads as 0 in simulation when CSRStatus has fields.
 2023-10-27 13:05:51 +11:00
Florent Kermarrec 577674bff2 test: Add minimal test_spi_mmap with simulation of SPIMaster. 2023-08-04 17:51:22 +02:00
enjoy-digital 33fbf558a2
Merge branch 'master' into avalon-burst-test 2023-05-10 11:12:30 +02:00
Hans Baier 71a0e398a7 Avalon2Wishbone test: assert readdatavalid on bursts 2023-05-10 04:05:16 +07:00
Hans Baier f00eb4e112 AvalonMM2Wishbone: use same addressing on avalon and wishbone, leave address translation to the user 2023-05-09 15:26:27 +07:00
Florent Kermarrec 8e1a3880d3 interconnect/avalon: Switch to directory/python package and split mm/st. 
Similarly to what is done for AXI and will avoid too complex/large files.
 2023-05-08 09:25:16 +02:00
Hans Baier c5c7e86cca
WIP AvalonMM interface and Avalon to Wishbone Bridge (#1674) 
Add initial AvalonMM interface and AvalonMM2Wishbone.
 2023-05-08 08:42:10 +02:00
Joel Stanley 3922359ba1 test: Reinstate microwatt and neorv32 
They appear to be passing CI again.

Signed-off-by: Joel Stanley <joel@jms.id.au>
 2023-02-27 17:46:41 +10:30
Florent Kermarrec 5c922320a0 test/test_cpu: Disable NeoRV32 in CI (Seems to be broken with Verilator update). 2023-01-23 08:44:57 +01:00
Florent Kermarrec 461b48fbaa test/test_cpu: Disable microwatt test for now since seems broken (GHDL issue). 
Will need to be investigated:
https://github.com/enjoy-digital/litex/actions/runs/3900056883/jobs/6662146988

Command line:
ghdl --synth --out=verilog --std=08 --no-formal /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/decode_types.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/wishbone_types.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/utils.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/common.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/helpers.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/nonrandom.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/fetch1.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/cache_ram.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/plrufn.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/dcache.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/icache.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/insn_helpers.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/predecode.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/decode1.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/control.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/decode2.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/register_file.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/crhelpers.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/cr_file.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/ppc_fx_insns.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/logical.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/rotator.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/countbits.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/execute1.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/loadstore1.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/divider.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/fpu.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/pmu.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/writeback.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/mmu.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/core_debug.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/core.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/multiply.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/multiply-32s.vhdl /home/runner/work/litex/litex/litex/soc/cores/cpu/microwatt/microwatt_wrapper.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/decode_types.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/wishbone_types.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/utils.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/common.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/helpers.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/nonrandom.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/fetch1.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/cache_ram.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/plrufn.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/dcache.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/icache.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/insn_helpers.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/predecode.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/decode1.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/control.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/decode2.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/register_file.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/crhelpers.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/cr_file.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/ppc_fx_insns.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/logical.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/rotator.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/countbits.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/execute1.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/loadstore1.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/divider.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/fpu.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/pmu.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/writeback.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/mmu.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/core_debug.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/core.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/multiply.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/multiply-32s.vhdl /home/runner/work/litex/litex/litex/soc/cores/cpu/microwatt/microwatt_wrapper.vhdl -e microwatt_wrapper
Exception SYSTEM.ASSERTIONS.ASSERT_FAILURE raised
Exception information:
raised SYSTEM.ASSERTIONS.ASSERT_FAILURE : elab-vhdl_annotations.adb:1401
Call stack traceback locations:
0x7fc79b8b0542 0x5631cf7cd3d0 0x5631cf7c8bf1 0x5631cf7c9219 0x5631cf7c93d2 0x5631cf7c977f 0x5631cf7ca0d3 0x5631cf7ca21a 0x5631cf7c9c41 0x5631cf7cbc0c 0x5631cf889270 0x5631cf97faf6 0x5631cf857fb0 0x5631cf988b5a 0x5631cf6d43d7 0x7fc79b432d8e 0x7fc79b432e3e 0x5631cf6d2f83 0xfffffffffffffffe
 2023-01-12 11:43:17 +01:00
Florent Kermarrec 497eac09a0 test/test_axi/test_axi_width_converter: Rename and cleanup. 2022-12-08 21:39:08 +01:00
Florent Kermarrec 0f95d04052 test/test_axi/test_axi_width_converter: Switch to DUT. 2022-12-08 18:54:59 +01:00
Florent Kermarrec a54d5180ba test/test_axi/test_axi_width_converter: Use address_width on Wishbone.Interface to simplify. 2022-12-08 16:23:15 +01:00
Joel Stanley b30dd0b5c6 test_cpu: Add NeoRV32 to tested CPUs 
With CI supporting GHDL to convert VHDL to Verilog the neorv32
simulation can be tested.

Fixes https://github.com/enjoy-digital/litex/issues/1320

Signed-off-by: Joel Stanley <joel@jms.id.au>
 2022-11-21 15:20:49 +10:30
Joel Stanley b0b57491bb test_cpu: Add Microwatt to tested CPUs 
Now that LiteX can convert from VHDL to Verilog using GHDL, and the
required dependencies are installed in the CI environment, start testing
Microwatt.

Signed-off-by: Joel Stanley <joel@jms.id.au>
 2022-11-14 22:09:47 +10:30
Joel Stanley b340b86975 test_cpu: Set number of verilator jobs 
By default verilator will be built with -j with no arguments, spawning
many processors. This causes large designs to failure in CI (probably
due to exhausting the memory of the build box):

 Error: Process completed with exit code 143.

Set the number of jobs to the number of CPUs in the system. This allows
designs such as Microwatt to build in CI.

Signed-off-by: Joel Stanley <joel@jms.id.au>
 2022-11-14 22:05:54 +10:30
Florent Kermarrec ec126f0e4d test/test_cpu: Move ibex to untested_cpus since seems to be broken since 2022.11.12. 2022-11-14 09:51:37 +01:00
Florent Kermarrec a10b1fd1e6 gen/common/Reduce: Add ADD support. 2022-10-28 19:13:27 +02:00
Florent Kermarrec 5106fd43fc gen/common: Add Reduction function (To avoid using Python's reduction directly which is messy/confusing). 2022-10-28 15:13:17 +02:00
Florent Kermarrec a57f0640cc soc/interconnect/csr: Add optional support fixed CSR mapping. 
By default, location is still automatically determined but it's now possible to
specific locations:

The following module:

class MyModule(Module, AutoCSR):
    def __init__(self):
        self.csr0 = CSRStorage()
        self.csr1 = CSRStorage(n=0)
        self.csr2 = CSRStorage(n=2)

built on a SoC with 32-bit CSR data-width will have the following CSR mapping:
- 0x00 : csr1
- 0x04 : csr0
- 0x08 : reserved
- 0x0c : csr2
 2022-10-21 14:47:59 +02:00
Florent Kermarrec d36f98bf45 axi/axi_full: Simplify by switching AXI channels to AXIStreamInterface. 2022-09-15 15:52:03 +02:00
Florent Kermarrec 3b714c8145 test: Add minimal test_axi_stream test (Just syntax check for now). 2022-09-08 11:53:05 +02:00
Florent Kermarrec a6acfb9a37 stream/Buffer: Integrate PipeValid/PipeReady (both configurable) and add tests. 
Allow selecting pipelining of valid/data or/and ready and creating a full Skid Buffer
(Pipeline of both valid/data and ready).
 2022-09-07 08:59:37 +02:00
Florent Kermarrec 74467e3b38 test/test_axi/test_axi_width_converter: Switch to DUT_ref (To avoid breaking CI). 
We'll switch back to DUT when AXI Converter will be fixed.
 2022-07-25 12:34:38 +02:00
Ilia Sergachev 982f94ba8d test: add axi 64b to 32b conversion test 2022-07-25 00:20:48 +02:00
Ilia Sergachev 65d5161408 test/axi_lite: parametrize address and data width in another test; add another test call with 64b data width 2022-07-20 02:44:57 +02:00
Ilia Sergachev bffd59726c test/axi_lite: rename a test for clarity; parametrize address and data width; add another test call with 64b data width 2022-07-20 02:43:43 +02:00
Florent Kermarrec 9c3663f3d2 test/test_cpu: Re-enable cv32e40p/marocchino. 2022-06-29 11:15:48 +02:00
enjoy-digital ec9d1c4fd0
CI: Disable more CPUs. 2022-06-27 22:43:01 +02:00
Florent Kermarrec f898423390 test/test_cpu: Diable mor1kx/picorv32 for now due to issue with newer Verilator. 2022-06-27 19:54:50 +02:00
Robert Szczepanski cbd873a33e test: FifoSyncMacro: Use F4PGA instead of deprecated Symbiflow 2022-06-17 16:27:25 +02:00
Florent Kermarrec 3f8cafeb58 test/test_cpu: Disable cva5 and enable marocchino/mor1kx. 2022-06-03 17:14:52 +02:00
Florent Kermarrec c0fc342823 test/test_cpu: Simplify using subTest/lists, test more RISC-V CPUs and comments for untested CPUs. 
Also use --opt-level=O0 to reduce compilation time (execution is a bit slower but since we are only
executing the BIOS here, total test time is still reduced).
 2022-06-03 16:16:21 +02:00
Florent Kermarrec 69451fad09 test/test_cpu: Disable test_cva6 for now since seems to be failing. 2022-05-25 09:32:30 +02:00
Massimiliano Giacometti c95ddbbff8 UART_POLLING 2022-05-19 15:07:46 +02:00
Robert Szczepanski 22abe1d543 Add tests for FIFOSyncMacro 2022-04-27 10:53:52 +02:00
Rafal Kolucki 8c1bc139ab soc/interconnect/wishbone: Cleanup in burst cycles support logic 2022-04-12 15:32:29 +02:00
Rafal Kolucki ad46a57403 test/test_wishbone: Add test for Wishbone SRAM constant address burst cycle 2022-04-12 14:06:22 +02:00
Rafal Kolucki cdd216f692 test/test_wishbone: Add basic test for SRAM with burst cycles support 
Tests incrementing address burst cycle with linear and wrapped increments.
Only 4-beat wrap burst is tested in `test_sram_burst_wrap` test.
 2022-04-12 14:06:22 +02:00
Florent Kermarrec ed6a6a83a9 litex_setup: Switch to manual install for Amaranth/Minerva (No longer supporting Python 3.6). 
We could revert when upgrading LiteX python requirement.
 2022-04-04 15:39:05 +02:00
Florent Kermarrec d39c3ed626 soc/cores/led: Review/Rework #1265. 
- Split FSM in Main FSM/Xfer FSM to decouple Led data read from bit xfer and do read during xfer.
- Only keep optimization that are easily to understand.
- Default to new WS2812 revision (Since also works on old revision).
- Test 75/50/25MHz sys_clk_freq.
 2022-04-04 15:24:54 +02:00
Wolfgang Nagele 67369403a9 Improve WS2812 timings and add different hardware revision support 2022-04-03 17:09:56 +02:00
Florent Kermarrec 6ef96b17bc soc/interconnect/csr: Fix CSRConstant read method (And add test_csr_constant to test_csr). 2022-03-21 15:21:08 +01:00
Florent Kermarrec dbde036162 soc/cores: Re-integrated generic/portable HyperBus/HyperRAM core from LiteHyperBus. 
The generic version of the HyperRAM core is simple enough to be directly integrated in LiteX
which avoid an additional dependency.
 2022-03-01 09:11:55 +01:00
Florent Kermarrec f62eca77e3 test/test_axi: Minor cleanups. 2022-02-17 15:13:05 +01:00
Florent Kermarrec 77c6cdd78e cores/clocks/lattice_ecp5: Rename ECP5Delay to ECP5DynamicDelay and adapt style for consistency. 2022-01-25 11:09:15 +01:00
Florent Kermarrec ea6bb3dd80 test/test_clock: Add minimal ECP5Delay test (syntax), rename tests with underscore. 2022-01-25 10:49:33 +01:00
Florent Kermarrec e50ff33c6e test/test_cpu: Disable Minerva test for now. 2021-12-13 16:51:23 +01:00