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913 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq ac5271e80e sim: truncate case test value 2015-10-19 20:08:46 +08:00
Sebastien Bourdeauducq ee283575d8 test: fix divider testbench 2015-10-19 19:41:18 +08:00
Sebastien Bourdeauducq 1f89900b16 sim: generators are also iterables... 2015-10-19 19:21:20 +08:00
Sebastien Bourdeauducq 02d804feab sim: accept iterables as generator list 2015-10-19 19:18:17 +08:00
Sebastien Bourdeauducq 0999a17319 verilog, sim: accept iterables in FHDL statements 2015-10-19 19:17:26 +08:00
Sebastien Bourdeauducq 4d9b2fff63 genlib/fsm: fix return value of _get_register_control 2015-10-19 19:03:43 +08:00
Sebastien Bourdeauducq a824046bbc Revert "sim/core: fix Cat bitshift" 
This reverts commit 6d6f91a02b.
 2015-10-19 16:08:42 +08:00
Sebastien Bourdeauducq 6d6f91a02b sim/core: fix Cat bitshift 2015-10-19 16:07:45 +08:00
Sebastien Bourdeauducq 28962ff438 sim/core: truncate evaluated values before test in If 2015-10-19 15:58:21 +08:00
Sebastien Bourdeauducq ec80f0fa7e build/vivado: quote paths in Tcl (prevents problems with \ on Windows) 2015-10-19 09:40:44 +08:00
Sebastien Bourdeauducq 4acb7bc662 sim: support execution of nested statement lists (typo) 2015-10-15 13:53:04 +08:00
Sebastien Bourdeauducq 3b7f1264f1 sim: support execution of nested statement lists 2015-10-15 13:52:24 +08:00
Sebastien Bourdeauducq 48d22a7588 genlib/fifo: width_or_layout -> width 2015-10-14 21:36:44 +08:00
Sebastien Bourdeauducq 8817716d5f test/divider: subtests 2015-10-13 18:39:41 +08:00
Sebastien Bourdeauducq e0899c1424 sim: make sure replaced memory signals are always in VCD signal set 2015-10-05 12:24:32 +08:00
Sebastien Bourdeauducq 6c01f80fc5 genlib/fifo: add missing imports 2015-09-30 18:58:46 +08:00
Sebastien Bourdeauducq 0c1e1c9769 test/fifo: do not use Record 2015-09-30 17:06:31 +08:00
Sebastien Bourdeauducq 4451bb20e5 genlib/fifo: remove Record support 2015-09-30 16:39:33 +08:00
Sebastien Bourdeauducq 913558ab19 build: stop at the first failed Quartus command 2015-09-29 15:53:18 +08:00
Sebastien Bourdeauducq 5e45b6ced6 build: add missing import for Lattice Diamond 2015-09-29 15:44:57 +08:00
Sebastien Bourdeauducq 6d2d70d879 fhdl/FullMemoryWE: fix clocking 2015-09-29 13:12:27 +08:00
Sebastien Bourdeauducq b4c5ffc1ba fhdl: typecheck ClockSignal and ResetSignal arguments 2015-09-29 13:11:40 +08:00
Sebastien Bourdeauducq 7c9a7ee757 build: cleanup 2015-09-28 20:34:35 +08:00
Sebastien Bourdeauducq 09003a55e1 fhdl/specials/Tristate: handle i=None 2015-09-26 21:49:12 +08:00
Sebastien Bourdeauducq e136352e8f fhdl/structure: relax type requirements for Array elements 2015-09-26 21:47:33 +08:00
Sebastien Bourdeauducq 808cf06add fhdl: replace flen with len 2015-09-26 18:45:10 +08:00
Sebastien Bourdeauducq fa1e8cd822 wrap expressions in Specials 2015-09-26 16:45:13 +08:00
Sebastien Bourdeauducq 8f42b6f352 fhdl: introduce wrap function 2015-09-26 15:36:28 +08:00
Sebastien Bourdeauducq 67903494bf fhdl: export DUID 2015-09-26 13:46:57 +08:00
Sebastien Bourdeauducq 33f344b92a fsm: NextState and NextValue should derive from _Statement 2015-09-23 22:38:10 +08:00
Sebastien Bourdeauducq 8534562185 sim: fix slice assign 2015-09-22 20:33:44 +08:00
Sebastien Bourdeauducq 31ffa8c18f fsm: support complex targets in NextValue. Closes #27. 2015-09-22 16:55:24 +08:00
Sebastien Bourdeauducq 1857ec6c32 fhdl/namer: support ClockSignal and ResetSignal. Closes #24 2015-09-22 14:30:16 +08:00
Sebastien Bourdeauducq 2c1553fea2 sim: insert resets, support ClockSignal and ResetSignal 2015-09-21 22:13:36 +08:00
Sebastien Bourdeauducq 99af825a5a sim: drive clock signals 2015-09-21 21:53:41 +08:00
Sebastien Bourdeauducq a67b4baa0c sim: VCD output support 2015-09-21 21:20:31 +08:00
Sebastien Bourdeauducq 34ce6b077f verilog: remove unneeded import 2015-09-21 21:19:58 +08:00
Sebastien Bourdeauducq 1767eef9cb fhdl/visit: support Constant 2015-09-20 16:10:17 +08:00
Sebastien Bourdeauducq 7f767095ec sim: support generators yielding statements 2015-09-20 15:04:15 +08:00
Sebastien Bourdeauducq 320dffb4ac sim: memory access from generators 2015-09-20 14:52:26 +08:00
Sebastien Bourdeauducq 59802bec76 fhdl/structure: add missing init 2015-09-20 14:46:30 +08:00
Sebastien Bourdeauducq 8bbfaa01fc sim: memory support 2015-09-19 23:21:46 +08:00
Sebastien Bourdeauducq 1861ae9d01 fhdl/specials: MemoryPort.clock should always be a ClockSignal 2015-09-19 23:21:24 +08:00
Sebastien Bourdeauducq 262fd50677 fhdl/simplify: add MemoryToArray 2015-09-19 23:20:57 +08:00
Sebastien Bourdeauducq 944a0b0480 test/fifo: convert to new API 2015-09-19 23:20:30 +08:00
Sebastien Bourdeauducq dcf4f7fef3 genlib/fifo: add missing import 2015-09-19 23:20:19 +08:00
Sebastien Bourdeauducq 9420aabc0d sim: support arrays, and cat+slice in assignment target 2015-09-19 14:56:26 +08:00
Florent Kermarrec 563231fdfb migen/genlib/cdc: fix BusSynchronizer 
ping/pong token can be lost when:
- source clock domain starts before destination clock domain.
- a clock domain stops.

This fix add a timeout to detect such situation and create another token.
 2015-09-19 12:21:54 +08:00
Sebastien Bourdeauducq bfcc8f9661 sim: remove unneeded import 2015-09-19 12:18:20 +08:00
Sebastien Bourdeauducq 84f98b4632 genlib/CRG: fix variable name conflict 2015-09-19 11:18:44 +08:00