351e654e9d
software/bios/sdram: flush dcache and l2 in memtest (otherwise we are partially testing the cache)
2015-06-23 09:01:34 +02:00
781869d6f9
software/libbase/system: fix flush_l2_cache
2015-06-19 09:00:14 +02:00
f44956bfca
soc/sdram: add L2_SIZE constant and avoid declaring an empty flush_l2_cache function when L2_SIZE is not defined
2015-06-19 08:39:37 +02:00
3b9f287bab
sdram: use wishbone cache as L2 cache and add optional L2 cache to Minicon
2015-06-17 15:30:30 +02:00
a8b9c126cd
spiflash: now using 64k sectors
2015-05-27 18:44:14 +08:00
3f7e161867
spiflash: cleanup unnecessary parenthesis
2015-05-27 18:44:14 +08:00
438a0856c5
misoclib/cpu: merge git.py in identifier
2015-05-02 18:42:33 +02:00
e8c01ff4aa
do more test with last changes fix small issues
2015-05-02 16:22:38 +02:00
8aa3fb3eb7
com/uart: add tx and rx fifos.
...
Since ressource usage is low with default depth of 16 (implemented in RAM LUTs) we don't keep old behaviour.
Tested successfully with BIOS and flterm.
2015-05-01 15:59:26 +02:00
1d9771f574
spiflash: use SoC defines, add write_to_flash function
2015-04-27 13:42:32 +08:00
0b1a2e1022
liteeth: do MII/GMII detection in gateware for gmii_mii phy
2015-04-26 18:08:07 +02:00
ae71bf2830
liteeth: fix and improve 10/100/1000Mbps speed auto detection
2015-04-26 14:54:53 +02:00
3710afe7fe
microudp.c: add #ifdef on ethmode (bios generation for gmii or mii was broken)
2015-04-12 20:59:50 +02:00
4abe8e1d9e
microudp: fix if (
2015-04-12 18:52:35 +02:00
515398634f
liteeth/phy/gmii_mii: add clock counter and use it in bios to select mode
2015-04-12 18:42:52 +02:00
c7361f1cdf
software/common.mak: fix alignment in quiet output
2015-04-03 17:43:29 +08:00
73d3b8487c
crt0-or1k: clean up indentation
2015-04-03 13:23:28 +08:00
63f14f3f30
libbase: implement flush_l2_cache for or1k
2015-04-02 16:47:03 +08:00
f4c35e358e
software/bios/sdram: small clean up
2015-03-27 18:24:19 +01:00
6245dd7b6f
software/bios/sdram: for now desactivate random on address test since it seems to trigger a L2 cache or LASMIcon bug on at least de0nano/minispartan6
...
Memtest sometimes reports 1 or 2 errors with de0nano/minispartan6 on this new test when used with LASMICON. Minicon seems fine. We will have to investigate on this issue.
2015-03-27 16:43:22 +01:00
f85a4f004b
software/bios/sdram: add random addressing to memtest
...
testing memories with linear access is not good enough. Adding random addressing allow us to detect more eventual issues on our L2 cache or SDRAM controller.
2015-03-27 15:49:16 +01:00
38d24b637e
software/bios/sdram: make seed_to_data static
2015-03-26 23:05:20 +01:00
e79a716425
software/bios/sdram: select the type of data we want to generate for memtest with TEST_RANDOM_DATA (debugging hardware is easier with a simple counter)
2015-03-26 22:16:31 +01:00
257706517e
software/memtest: remove Mixxeo/M1 hardcoded values in bandwidth computation
2015-03-26 00:01:42 +01:00
1fc24e66dc
sofware/memtest: use MAIN_RAM_SIZE from mem.h
2015-03-25 19:00:07 +01:00
94b62eff8b
libcompiler-rt: add ucmpdi2.o
2015-03-25 17:57:42 +01:00
69e9032d49
sofware/memtest: update bandwidth registers
2015-03-25 17:25:39 +01:00
6492ef1efa
linker-sdram.ld: sdram mem region is now called main_ram
2015-03-25 16:45:19 +01:00
9bc71f374a
rename sdram mapping to main_ram
2015-03-21 21:01:46 +01:00
b75e4b237d
software/bios/memtest: add data bus test (0xAAAAAAAA, 0x55555555) on a small portion of the test zone.
...
we now need to add another random addressing test to avoid linear access on L2 cache
2015-03-21 20:29:15 +01:00
84b631c929
liteeth/mac/core: add with_padding option (enabled by default) and change with_hw_preamble_crc option to with_preamble_crc
2015-03-19 14:52:02 +01:00
473997df26
cpuif: add CSR_ prefix to CSR base addresses (avoid conflicts between CSR and mems bases)
2015-03-02 16:52:17 +01:00
8280acd3a7
sdram: only keep frontend logic and sdram core declaration in soc/sdram.py, move other logic to sdram/core
2015-03-02 12:17:49 +01:00
0980becb56
sdram: improve memtest by adding 2 different writes/reads
...
doing only a write and read is not enough: if we reloaded a fpga with write that is not working after functional fpga, it would not trigger an error.
2015-03-02 10:52:22 +01:00
2c51adcd68
misoclib: better organization (create cores categories: cpu, mem, com, ...)
2015-02-28 09:40:44 +01:00
07b9cabd0d
gensoc: make it more generic (a SoC does not necessarily have a CPU)
2015-02-27 16:39:00 +01:00
be0eb8d265
use cachesize reported in wishbone2lasmi
2015-02-27 14:13:38 +01:00
edb1622668
spiflash: BB write support
2014-11-27 23:10:39 +08:00
603c2641bb
new Ethernet MAC
2014-11-20 16:47:22 -08:00
09773df186
software: make compiler-rt a submodule
2014-11-06 18:00:28 -08:00
410f250d2a
software: remove setjmp
2014-09-23 21:57:05 +08:00
14d53526be
libbase: use __builtin_setjmp and __builtin_longjmp
2014-09-21 17:43:17 +08:00
36434b62f0
sdram: merge DFII_PIX_RDDATA_SIZE and DFII_PIX_WRDATA_SIZE
2014-09-03 15:02:38 +08:00
2388bfabc3
bios: support DDR3 write leveling and read calibration. This makes the full DDR3 SODIMM work on the KC705.
2014-09-03 14:25:26 +08:00
6decb357f1
bios: add sdrrderr
2014-09-01 15:23:37 +08:00
57335bdf3f
bios: add DQ filtering to sdrrd, add sdrrdbuf command
2014-09-01 14:58:58 +08:00
a2096ff083
libcompiler-rt: add moddi3
2014-08-28 16:54:12 +08:00
0ebdf2be6d
bios/sdram: cleanup
2014-08-08 21:57:58 +08:00
b61dced909
bios/sdram: set ODT and RESET_N through DFII
2014-08-08 21:57:42 +08:00
8deadc5760
dfii: drive ODT and RESET_N
2014-08-08 21:56:35 +08:00
293ac09673
sdramphy/bios: make sdrrd/sdrwr generic
2014-08-08 19:25:10 +08:00
213cb43ae5
Keep only basic SoC designs in MiSoC
2014-08-03 12:30:15 +08:00
8349543732
style
2014-07-05 18:56:20 +02:00
2bb821c571
crt-or1k: trim useless exception vectors
2014-07-05 18:53:23 +02:00
4c2a2090b1
libbase: remove crt during make clean
2014-06-01 23:17:43 +02:00
b26ac465bd
crt0: remove macadress for or1k as well
2014-05-24 10:43:50 +02:00
6deeca064f
bios/crt0.S: remove unused macaddr, add syscall handler stub
2014-05-24 10:41:54 +02:00
ed902bfcdf
crt: add umoddi3
2014-05-24 10:38:55 +02:00
dc2024f54d
bios: remove references to 'DDR' SDRAM, as we also support SDR SDRAM
2014-05-23 21:31:26 +02:00
398608e997
bios: fill delay slot in boot_helper
2014-05-14 16:08:25 +02:00
13e74b8b4f
software: factorize exception_handler
2014-05-14 15:01:38 +02:00
edf567a0cd
bios: fix boot for or1k
2014-05-14 15:01:02 +02:00
1c08aeb21c
Initial mor1kx (OpenRISC) support
...
Based on milkymist-ng-mor1kx by Stefan Kristiansson
2014-05-14 10:24:56 +02:00
11be0a27fc
fix minimac bases addresses
2014-05-12 19:19:34 +02:00
87a8504304
Refactor CRC tools
2014-04-19 00:01:29 +02:00
93f02a8cf4
tools: replace mkmscimg with mkmscimg.py (mkmscimg.c was platform dependent)
2014-04-18 20:22:42 +02:00
f76da70cda
software/libcompiler-rt: adapt to new upstream directory organization
2014-04-08 15:29:23 +02:00
3882a07ae5
Add Python flasher
2014-02-28 09:40:49 -08:00
9e784fc82c
Generate mem.h from SoC description
2014-02-21 17:55:05 +01:00
fce46ac0ca
Simplify use of external targets/platforms/cores + add default platform in targets
2014-02-16 14:51:52 +01:00
a23dffd2c2
bios: update banner
2014-02-15 14:02:09 +01:00
f55943ae18
new action syntax for make.py + support xc3sprog
2014-02-15 14:01:50 +01:00
14b50dbb0c
videomixer: config system + store video resolution in flash
2013-11-30 23:07:19 +01:00
4ba796417d
software: do not attempt to build network/sdram drivers when cores are not present
2013-11-24 23:50:09 +01:00
d4063409e1
software/bios: infer flash start from linker
2013-11-24 23:45:03 +01:00
fca0b968e7
generate linker memory map, move all generated files into the same folder
2013-11-24 19:50:17 +01:00
bc2b4a888b
memtest: flush caches, display total error count, use ifdef instead of comment
2013-11-24 13:59:45 +01:00
7496ba6360
framebuffer: fix resynchronization after resolution change
2013-11-21 00:33:22 +01:00
f5ba0ac023
videomixer: select 1024x768 by default
2013-11-21 00:33:01 +01:00
f62615054d
videomixer: stick to 20x PLL configuration as 10x causes traditional spartan6 weirdness
2013-11-18 20:43:30 +01:00
a75be2e5dd
videomixer: reconfigure PLL on resolution change
2013-11-18 20:37:45 +01:00
72001addcb
videomixer: add PLL dump command
2013-11-18 20:37:27 +01:00
6fc03946be
videomixer: add PLL control code
2013-11-18 20:37:10 +01:00
8b82575861
dvisampler: hold PLL in reset when disabled
2013-11-18 20:36:30 +01:00
8f164d0d7b
videomixer: reduce debug output
2013-11-17 23:40:42 +01:00
64bfca56b4
videomixer: add more video modes
2013-11-16 17:41:03 +01:00
ba15f1581f
videomixer: flush L2 after CPU framebuffer write
2013-11-16 16:27:58 +01:00
c9e99dfca9
bios: flushl2 command
2013-11-16 16:27:34 +01:00
c3d0985fb2
add L2 cache size in identifier + function to flush L2
2013-11-16 16:27:21 +01:00
940341b4bf
videomixer: fix stray DMA detection
2013-11-16 13:53:38 +01:00
d225bdf362
videomixer: clear framebuffers
2013-11-15 11:25:58 +01:00
a5d9f72901
videomixer: check resolution and frame length
2013-11-13 18:57:39 +01:00
1582bad2d6
videomixer: filter PLL lock output
2013-11-13 16:50:09 +01:00
1a28690fa0
microudp: fix udp txlen
...
* the preample length 8 is already included in sizeof(struct
ethernet_header)
* the minimum packet size is 64, exluding fcs and including
preample it is 68 (the arp functions are correct)
2013-11-12 19:05:15 +01:00
69568adb8e
videomixer: support resolution change at runtime
2013-11-11 23:20:21 +01:00
593867b92a
videomixer: add more video modes
2013-11-11 22:16:56 +01:00
c8da400af0
videomixer: compute best m/d value for pixel clock synthesizer
2013-11-11 21:30:12 +01:00
132b6ce87d
videomixer: set established timing bits in EDID
2013-11-11 18:56:13 +01:00
3ba9fbefd5
videomixer: generate EDID
2013-11-11 17:52:07 +01:00
f5211aff30
videomixer: add EDID manipulation routines
2013-11-10 23:50:18 +01:00
Florent Kermarrec
Yann Sionneau
Sebastien Bourdeauducq
Robert Jordens
Sebastien Bourdeauducq