Florent Kermarrec
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ddae41f2e4
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liteeth/phy/mii: simplify LiteEthPHYMIITX using Converter
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2015-04-12 15:34:56 +02:00 |
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Florent Kermarrec
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8c722db54e
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liteeth/phy/mii: assign tx_er only if exists (as it's done on GMII)
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2015-04-12 14:43:35 +02:00 |
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Florent Kermarrec
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4329e3e1b9
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liteeth/phy/mii: allow use of MII phy on GMII/MII chips that do not have phy clock provided by the FPGA (tested on KC705)
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2015-04-12 14:28:17 +02:00 |
Sebastien Bourdeauducq
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603a4ef51e
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liteeth: adapt to new ModuleTransformer
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2015-04-10 11:42:25 +08:00 |
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Florent Kermarrec
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03aa972bb6
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lite*: finish ModuleTransformer adaptations (need to be tested on board)
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2015-04-08 23:27:22 +02:00 |
Robert Jordens
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66f8dcbfaf
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lite*: adapt to new ModuleTransformer semantics
NOTE: There is loads of duplicated code between the lite*
modules that should be shared.
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2015-04-04 19:17:24 +08:00 |
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Florent Kermarrec
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dcdf5df4de
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adapt LiteEth to new SoC
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2015-04-01 22:50:29 +02:00 |
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Florent Kermarrec
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9107710f03
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litexxx cores: use default baudrate of 115200 for all tests
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2015-03-20 12:22:53 +01:00 |
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Florent Kermarrec
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84b631c929
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liteeth/mac/core: add with_padding option (enabled by default) and change with_hw_preamble_crc option to with_preamble_crc
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2015-03-19 14:52:02 +01:00 |
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Florent Kermarrec
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6bdf60567c
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liteeth/mac/core: fix hw_preamble_crc register generation
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2015-03-19 13:03:27 +01:00 |
|
Florent Kermarrec
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236ea0f572
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liteeth: use bios ip_address in example designs
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2015-03-18 18:18:43 +01:00 |
|
Florent Kermarrec
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a266deb58e
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LiteXXX cores: fix frequency print in test/test_regs.py
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2015-03-17 16:01:25 +01:00 |
|
Florent Kermarrec
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d2cb41bc63
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LiteXXX cores: convert port parameter to int if is digit in test/make.py
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2015-03-17 15:58:21 +01:00 |
|
Florent Kermarrec
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2327710387
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liteeth/phy/gmii : set tx_er to 0 only if it exits
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2015-03-17 12:24:06 +01:00 |
|
Florent Kermarrec
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408d0fd2dd
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liteeth: use default programmer in make.py
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2015-03-17 12:12:21 +01:00 |
|
Florent Kermarrec
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ec6ae75065
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liteeth: use CRG from Migen in base example
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2015-03-17 12:11:51 +01:00 |
|
Florent Kermarrec
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faf185d58d
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liteeth: make gmii phy generic
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2015-03-16 23:04:37 +01:00 |
|
Florent Kermarrec
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c3c7f627d9
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liteeth/phy: typo (thanks sb)
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2015-03-12 21:54:10 +01:00 |
|
Florent Kermarrec
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767d45727a
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uart/liteeth: only import the phy we are going to use (UARTPHYSim cannot be imported on Windows since based on pty).
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2015-03-12 16:57:38 +01:00 |
|
Florent Kermarrec
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6cbf13036b
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liteeth/mac: fix padding limit (+1), netboot OK with sim platform
|
2015-03-09 20:59:34 +01:00 |
|
Florent Kermarrec
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47cceea222
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liteeth/mac: use Counter in sram and move some logic outside of fsms
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2015-03-09 20:22:14 +01:00 |
|
Florent Kermarrec
|
b10836a8eb
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liteeth/phy/sim: create ethernet tap in __init__ and destroy it in do_exit
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2015-03-09 17:21:29 +01:00 |
|
Florent Kermarrec
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360c849f21
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liteeth: fix cnt_inc in IDLE state (we should wait sop to inc counter)
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2015-03-09 13:23:39 +01:00 |
|
Florent Kermarrec
|
5dbd8af4be
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liteeth: do not insert CRC/Preamble in simulation to allow direct connection to ethernet tap
|
2015-03-09 13:23:37 +01:00 |
|
Florent Kermarrec
|
95fa753149
|
liteeth: add phy autodetect function (phy can still be instanciated directly)
|
2015-03-06 10:10:34 +01:00 |
|
Florent Kermarrec
|
52f1c45407
|
LiteXXX cores: fix test_reg.py
|
2015-03-04 23:13:14 +01:00 |
|
Florent Kermarrec
|
1d4dc45436
|
LiteXXX cores: use format in prints
|
2015-03-03 10:29:28 +01:00 |
|
Florent Kermarrec
|
649cdeb265
|
liteXXX cores: use new uart and import FlipFlop/Counter/Timeout from Migen
|
2015-03-01 16:48:41 +01:00 |
|
Florent Kermarrec
|
c21a7956c8
|
liteXXX cores: remove Identifier duplication
|
2015-03-01 11:24:58 +01:00 |
|
Florent Kermarrec
|
67ca0da1d9
|
liteXXX cores: share same methodology for on-board tests
|
2015-03-01 11:21:12 +01:00 |
|
Florent Kermarrec
|
b32a0e6f9e
|
liteeth: create example design derived from SoC that can be used on all targets with Ethernet pins
|
2015-02-28 23:33:00 +01:00 |
|
Florent Kermarrec
|
b34be816ec
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liteXXX cores: remove setup.py and relative paths (we will install misolib of use PYTHON_PATH)
|
2015-02-28 22:23:48 +01:00 |
|
Florent Kermarrec
|
5c43d4d091
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litescope: create example design derived from SoC that can be used on all targets
|
2015-02-28 22:19:24 +01:00 |
|
Florent Kermarrec
|
0fd1b9df8d
|
liteXXX cores: remove redefinition of get_csr_csv
|
2015-02-28 21:45:05 +01:00 |
|
Florent Kermarrec
|
5bd1ab7fa1
|
liteXXX cores: update README and doc
|
2015-02-28 21:40:59 +01:00 |
|
Florent Kermarrec
|
69e869893d
|
remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future)
|
2015-02-28 11:36:15 +01:00 |
|
Florent Kermarrec
|
2c3e8a2804
|
liteeth: fix example design generation and remove VivadoProgrammer from platfom. (TODO: remove others duplicates)
|
2015-02-28 11:04:48 +01:00 |
|
Florent Kermarrec
|
df0ba1b03c
|
litescope: create example_designs directory
|
2015-02-28 10:42:12 +01:00 |
|
Florent Kermarrec
|
c4ebf244a1
|
litescope: move files and modify import to misoclib.tools.litescope
|
2015-02-28 10:33:46 +01:00 |
|
Florent Kermarrec
|
2c51adcd68
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misoclib: better organization (create cores categories: cpu, mem, com, ...)
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2015-02-28 09:40:44 +01:00 |