175618bcb4
use csr_data_width of 32 to speed up data mila upload
2015-01-16 20:57:01 +01:00
083bd54121
global clean up
...
- remove initial sims
- remove SATAPHYDeviceCtrl
- rename to LiteSATA
- rename test to bist
2015-01-16 20:26:15 +01:00
e90d97e9c2
phy: remove GTXE2_COMMON (no longer need since it was a Vivado bug that is now fixed)
2015-01-16 19:25:35 +01:00
d13366dd2d
bist: use hardware counter for speed calc and remove loops mode
2015-01-16 18:48:34 +01:00
7ccc5f5274
link/cont: improve timing
2015-01-16 18:13:07 +01:00
1170a1070b
add need_reset from controller to request system reset when SATA is not locked
2015-01-15 00:56:47 +01:00
788546c6ae
add frontend and improve BIST
2015-01-14 15:47:13 +01:00
62f55e32cf
use new submodules/specials/clock_domains automatic collection
2015-01-12 13:14:26 +01:00
4f38b0ef6e
improve timings with BufferizeEndpoints
2015-01-08 22:59:31 +01:00
4deda89dcb
simplify bist
2015-01-07 22:15:57 +01:00
1c03f72252
command: add robustness and simplify RX path
2015-01-07 18:49:10 +01:00
aed1064465
command: replace SyncFIFO with Buffer for cmd_buffer
2015-01-06 17:03:27 +01:00
a450079866
command: add support for larger DMAs
2015-01-06 16:48:19 +01:00
c08c0ffc4e
link: check CRC on RX path
2014-12-25 17:15:35 +01:00
5575ecbcb2
test: fix link_tb and bist_tb
2014-12-25 12:28:06 +01:00
7efaef485f
command: remove returns to IDLE state (will be better to add a timeout for a transfer and reset the fsm).
2014-12-24 15:08:06 +01:00
7df1d75dee
use max_count of 16 and clean up
2014-12-23 23:19:48 +01:00
3e5a4ab097
add wr_only and rd_only mode to BIST (to test speed) and switch to 100MHz system clock
2014-12-23 20:41:13 +01:00
678ee33af4
improve BIST and clean up (remove support of identify command and debug code)
2014-12-23 19:27:52 +01:00
38d3f3697b
test bist at high speed(working)
2014-12-23 01:39:41 +01:00
5e513c25c2
link: fix rx path
2014-12-22 20:58:38 +01:00
c17159754c
add test_read / test_write (HOST<-->HDD transfers OK for the 3 tests, rx data seems to be stuck in link of command layer)
2014-12-20 16:50:34 +01:00
9dc6903c55
add identify device to command_tb and revert endianness (seems conform with Lecroy SATA Protocol suite samples)
...
it seems endianness is correct by is only printed in LSB first in Lecroy software
2014-12-20 13:26:07 +01:00
706fcb536d
change FIS endianness (seems to be little endian)
2014-12-20 12:58:37 +01:00
d368a89bbf
fix ack in idle in some fsm (implementation behaviour different from simulation)
2014-12-20 01:26:02 +01:00
35050ece9f
add fsms to mila for debug
2014-12-20 00:03:03 +01:00
68a7ff6dc2
use new submodules collection to expose more fsm an modules
2014-12-19 22:50:35 +01:00
ea245542c6
link: add parameter to disable CONT insertion (will ease debug)
2014-12-19 22:32:11 +01:00
ea2b06b285
fix phy datapath, first communications between SATACON and a HDD... :)
2014-12-19 22:20:41 +01:00
33eed1aa79
SATAPHYDatapathRX: use Converter and simplify
2014-12-19 17:27:44 +01:00
0ab7ca6f28
SATAPHYDatapathTX: use Converter and simplify
2014-12-19 17:13:03 +01:00
8bb40241fa
add phy_datapath_tb and start datapath simplification
2014-12-19 16:48:22 +01:00
9728a97834
add cont_tb and rewrite cont
2014-12-19 11:15:01 +01:00
9e14b1b051
use new implicit submodules collection and Pipeline
2014-12-19 01:35:18 +01:00
a8e1526407
link_tb: simplify using implicit submodules collect
2014-12-19 01:23:04 +01:00
4f22bc807a
make ctrl/datapath in phy vendor agnostics and simplify imports
2014-12-18 19:45:21 +01:00
9789a78aab
test: clean up imports
2014-12-18 16:45:12 +01:00
9ba9470974
test: create generic PacketStreamer/PacketLogger and use it in link_tb/command_tb
2014-12-18 13:15:39 +01:00
bcc0be10ee
phy: use vivado parameters and fix RX datapath (LSB first)
2014-12-17 23:49:55 +01:00
0f8f89a269
update clock constraints for SATA1 and use sys_clk of 200MHz
...
- data seems stable (mila capture) except when receive the ALIGN primtive from the device, we should maybe disable alignment on the HOST when link is ready...
2014-12-17 19:24:23 +01:00
5a16a5b46d
add very basic PHY stimulator (to see HDD behaviour when we send primitives)
2014-12-17 17:57:37 +01:00
2c0115262b
fix compilation and use new cpu_csr_regions
2014-12-17 12:03:52 +01:00
61bfbbff8a
improve check function
2014-12-17 08:58:02 +01:00
a71fa2f522
link_tb: fix cont regression
2014-12-15 20:00:19 +01:00
fadd21fae2
bist: add count to bist parameters
2014-12-15 19:48:22 +01:00
13d75d3933
move Counter to common and use it in all modules
2014-12-15 19:33:38 +01:00
d88b127abb
create SATACON and use it in bist_tb
2014-12-15 19:13:32 +01:00
ddb9d52270
bist: add ctrl_errors/data_errors and clean up
2014-12-15 19:04:45 +01:00
d193bd3321
hdd: improve debug print
2014-12-15 19:04:07 +01:00
707b43178b
add simple synthetizable BIST
2014-12-15 16:44:12 +01:00
Florent Kermarrec