Sebastien Bourdeauducq
|
e6e04a2e3a
|
framebuffer: prepare for DVI out
|
2013-09-17 18:15:22 +02:00 |
|
Sebastien Bourdeauducq
|
d421aae1a5
|
dvisampler: do more deserialization with the ISERDES
|
2013-09-14 20:50:27 +02:00 |
|
Sebastien Bourdeauducq
|
2459d9f559
|
top: DVI samplers and 2-channel FB on Mixxeo only
|
2013-09-13 23:07:46 +02:00 |
|
Sebastien Bourdeauducq
|
ea65aaaddd
|
s6ddrphy: cleanup
|
2013-07-17 13:58:58 +02:00 |
Florent Kermarrec
|
fb06d803e1
|
s6ddrphy: revert CAS LATENCY 3 (configurable CAS Latency was buggy)
|
2013-07-17 13:11:25 +02:00 |
|
Sebastien Bourdeauducq
|
be40cf178c
|
top: integrate memtest cores
|
2013-07-11 18:31:51 +02:00 |
|
Florent Kermarrec
|
60f1585fef
|
use Migen s6ddrphy, generate sdram init_sequence in cif.py
|
2013-07-10 19:56:09 +02:00 |
|
Sebastien Bourdeauducq
|
4cd360e6e1
|
Mixxeo support
|
2013-07-04 19:19:39 +02:00 |
|
Sebastien Bourdeauducq
|
e5737331ec
|
lasmicon: add FIFO at bankmachine input to ease timing
|
2013-06-17 23:33:57 +02:00 |
|
Sebastien Bourdeauducq
|
a04d53be07
|
top: raise frequency back to 83 1/3 MHz
|
2013-06-17 23:32:41 +02:00 |
|
Sebastien Bourdeauducq
|
3644d2a6ef
|
lasmicon: bandwidth monitoring
|
2013-06-15 12:51:11 +02:00 |
|
Sebastien Bourdeauducq
|
ce2f08844a
|
s6ddrphy: fix read latency
|
2013-06-11 16:02:34 +02:00 |
|
Sebastien Bourdeauducq
|
422c9a1db9
|
lasmi: reduce latencies by 1 cycle
|
2013-06-11 15:26:47 +02:00 |
|
Sebastien Bourdeauducq
|
91d7b656a9
|
Switch to LASMI, bug pandemonium
|
2013-06-11 14:18:16 +02:00 |
|
Sebastien Bourdeauducq
|
6d71e09281
|
cif: move to milkymist folder
|
2013-05-30 21:38:21 +02:00 |
|
Sebastien Bourdeauducq
|
fb3e61230b
|
Use new memory port API
|
2013-05-28 15:56:14 +02:00 |
|
Sebastien Bourdeauducq
|
611c4192b1
|
Use migen.fhdl.std
|
2013-05-22 17:10:13 +02:00 |
|
Sebastien Bourdeauducq
|
71cc2db867
|
Add GPIO buttons and LEDs
|
2013-05-16 17:43:20 +02:00 |
|
Sebastien Bourdeauducq
|
32c478af16
|
top: integrate ADC for pots
|
2013-05-13 15:45:06 +02:00 |
|
Sebastien Bourdeauducq
|
534dec62eb
|
First video mixing working (hacky)
|
2013-05-12 15:58:08 +02:00 |
|
Sebastien Bourdeauducq
|
e96b027dee
|
Framebuffer mixing
|
2013-05-10 21:03:55 +02:00 |
|
Sebastien Bourdeauducq
|
66b4bae7c8
|
top: connect dvisampler DMA IRQs
|
2013-05-08 22:31:42 +02:00 |
|
Sebastien Bourdeauducq
|
e2d15b169a
|
dvisampler: mostly working, very basic and slightly buggy DMA
|
2013-05-06 09:58:12 +02:00 |
|
Sebastien Bourdeauducq
|
4dcec32010
|
top: allocate one more ASMI port to framebuffer
|
2013-03-28 20:46:00 +01:00 |
|
Sebastien Bourdeauducq
|
8fd092ca12
|
crg: support VGA pixel clock reprogramming
|
2013-03-28 19:07:17 +01:00 |
|
Sebastien Bourdeauducq
|
1e860c7472
|
Use new Mibuild generic_platform API
|
2013-03-26 17:57:17 +01:00 |
|
Sebastien Bourdeauducq
|
fdf7f10f54
|
Automatically build CSR access functions
|
2013-03-25 14:42:48 +01:00 |
|
Sebastien Bourdeauducq
|
eaef3464e9
|
Instantiate DVI sampler core for both ports
|
2013-03-13 19:56:56 +01:00 |
|
Sebastien Bourdeauducq
|
a9b723568a
|
Use new module, autoreg and eventmanager Migen APIs
|
2013-03-10 19:32:38 +01:00 |
|
Sebastien Bourdeauducq
|
5649e88a90
|
Use Mibuild
|
2013-02-11 18:23:06 +01:00 |
|
Sebastien Bourdeauducq
|
0392dd8ac2
|
bank/csrgen: interface -> bus
|
2012-12-06 17:15:47 +01:00 |
|
Sebastien Bourdeauducq
|
fee70e9866
|
Use Wishbone SRAM component from Migen
|
2012-12-01 12:59:32 +01:00 |
|
Sebastien Bourdeauducq
|
7e2bc00c0a
|
Remove Constant
|
2012-11-28 23:18:53 +01:00 |
|
Sebastien Bourdeauducq
|
c86dd3cbef
|
Define clock domains instead of passing extra clocks as regular signals
|
2012-09-11 00:21:07 +02:00 |
|
Sebastien Bourdeauducq
|
5931c5eb59
|
Basic support for new clock domain and instance API
|
2012-09-10 23:47:06 +02:00 |
|
Sebastien Bourdeauducq
|
855eec776d
|
Add ASMIprobe core
|
2012-08-04 16:31:24 +02:00 |
|
Sebastien Bourdeauducq
|
6073f68b69
|
asmicon: simple selector option
|
2012-07-13 19:25:38 +02:00 |
|
Sebastien Bourdeauducq
|
b7aec21a47
|
top: use two slots for the framebuffer ASMI port
|
2012-07-12 19:40:49 +02:00 |
|
Sebastien Bourdeauducq
|
a52c3135c1
|
framebuffer: frame initiator
|
2012-06-17 17:22:02 +02:00 |
|
Sebastien Bourdeauducq
|
3a02524cc7
|
VGA framebuffer connections
|
2012-06-17 13:41:26 +02:00 |
|
Sebastien Bourdeauducq
|
f6f42293d1
|
Clock frequency detection
|
2012-05-22 13:23:44 +02:00 |
|
Sebastien Bourdeauducq
|
c01594f9fd
|
Common interrupt numbers
|
2012-05-21 19:52:41 +02:00 |
|
Sebastien Bourdeauducq
|
94245517f2
|
Add timer
|
2012-05-21 19:46:04 +02:00 |
|
Sebastien Bourdeauducq
|
8ad251c94c
|
Connect Ethernet IRQ
|
2012-05-20 23:48:41 +02:00 |
|
Sebastien Bourdeauducq
|
4e18e45686
|
Add Ethernet MAC
|
2012-05-20 00:30:03 +02:00 |
|
Sebastien Bourdeauducq
|
79124d822b
|
Identifier
|
2012-05-17 01:41:41 +02:00 |
|
Sebastien Bourdeauducq
|
141269b384
|
Get CSR base addresses from include file
|
2012-05-16 10:36:46 +02:00 |
|
Sebastien Bourdeauducq
|
19b1cc2529
|
Remove uses of pads, new constraints system
|
2012-04-02 19:22:17 +02:00 |
|
Sebastien Bourdeauducq
|
c26efa28ca
|
asmicon: multiplexer (untested)
|
2012-03-18 22:11:01 +01:00 |
|
Sebastien Bourdeauducq
|
0e00837f42
|
asmicon: move slot time to timing settings
|
2012-03-18 14:57:31 +01:00 |