d9b15e6ef6
cores: replace Timeout with new WaitTimer
2015-05-12 16:14:38 +02:00
fb5397aa82
uart: remove litescope dependency for UARTWishboneBridge and remove frontend
2015-05-09 16:08:20 +02:00
1fd189512f
liteusb/frontend/dma: remove +4 to length for CRC (we'll do it in core)
2015-05-08 23:10:08 +02:00
4d902b578c
liteusb/phy/ft245: rename "ftdi" clock domain to "usb"
2015-05-07 20:03:12 +02:00
da711ad5f1
liteusb: add simple example design with wishbone bridge and software to control it
2015-05-02 18:21:18 +02:00
e9ef11620f
liteusb/frontend/wishbone: use new packetized mode (allow grouping response in a single packet)
2015-05-02 16:22:45 +02:00
ff51bde7f0
liteusb/software/wishbone: optimize writes/reads (send a single packet for a command)
2015-05-02 16:22:40 +02:00
e8c01ff4aa
do more test with last changes fix small issues
2015-05-02 16:22:38 +02:00
3ebe877fd2
use similar names for wishbone bridges and move wishbone drivers to [core]/software
2015-05-02 16:22:30 +02:00
5e649a6577
litescope: add basic LiteScopeUSB2WishboneFTDIDriver (working but need to be optimized)
2015-05-01 20:45:04 +02:00
a8b8af220a
liteusb: add basic wishbone frontend (We could also reuse Etherbone in the future)
2015-05-01 20:44:59 +02:00
da0fe2ecfb
liteusb: refactor software (use python instead of libftdicom in C) and provide simple example.
...
small modifications to fastftdi.c are also done to select our interface (A or B) and mode (synchronous, asynchronous)
2015-05-01 16:22:26 +02:00
603b4cdc8c
liteusb: continue refactoring (virtual UART and DMA working on minispartan6)
...
- rename ft2232h phy to ft245.
- make crc optional
- fix depacketizer
- refactor uart (it's now only a wrapper around standard UART)
- fix and update dma
2015-05-01 16:11:15 +02:00
a6f290ac16
liteusb: add ft2232h_sync_tb
2015-04-28 19:05:34 +02:00
28c50112a4
liteusb: add FT2232HPHYAsynchronous PHY (Minispartan6+, Pipistrello), needs more simulations and on-board tests
2015-04-28 19:01:03 +02:00
30eed19283
liteusb: continue refactoring and add core_tb (should be almost OK)
2015-04-28 18:58:38 +02:00
dc8d844579
liteusb: begin refactoring and simplification (wip)
2015-04-27 15:22:49 +02:00
1e1f7ce30e
liteusb: more pep8 (when convenient), should be almost OK
2015-04-13 14:47:44 +02:00
f10e873063
liteusb: pep8 (E265)
2015-04-13 14:37:39 +02:00
5343537fc2
liteusb: pep8 (E225)
2015-04-13 14:34:36 +02:00
39df1ff636
liteusb: pep8 (E222)
2015-04-13 14:32:51 +02:00
9e3d3e7930
liteusb: pep8 (E231)
2015-04-13 14:30:48 +02:00
ce0e818d66
liteusb: pep8 (E201)
2015-04-13 14:29:44 +02:00
4974fd6bc9
liteusb: pep8 (E302)
2015-04-13 14:27:31 +02:00
cb473ddb6e
liteusb: pep8 (replace tabs with spaces)
2015-04-13 14:09:58 +02:00
20207c9c32
liteusb: give more generic names to modules: FtdiXXX becomes LiteUSBXXX, move PHY outside of core (builds on minispartan6)
2015-03-22 11:11:37 +01:00
c77562f44b
liteusb: make oe_n optional on ft2232h phy
2015-03-22 10:56:56 +01:00
ed5746a1fe
liteusb: fix imports
2015-03-22 10:56:29 +01:00
b305b7828a
sdram: create frontend dir and move dma_lasmi/memtest/wishbone2lasmi to it
2015-03-02 08:36:39 +01:00
5bd1ab7fa1
liteXXX cores: update README and doc
2015-02-28 21:40:59 +01:00
912573f5c9
liteusb: move files and modify import to misoclib.com.liteusb
2015-02-28 11:18:00 +01:00
b647fe5823
merge liteusb
2015-02-28 11:16:16 +01:00
Florent Kermarrec