Sebastien Bourdeauducq
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1f89900b16
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sim: generators are also iterables...
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2015-10-19 19:21:20 +08:00 |
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Sebastien Bourdeauducq
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02d804feab
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sim: accept iterables as generator list
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2015-10-19 19:18:17 +08:00 |
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Sebastien Bourdeauducq
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0999a17319
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verilog, sim: accept iterables in FHDL statements
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2015-10-19 19:17:26 +08:00 |
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Sebastien Bourdeauducq
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4d9b2fff63
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genlib/fsm: fix return value of _get_register_control
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2015-10-19 19:03:43 +08:00 |
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Sebastien Bourdeauducq
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a824046bbc
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Revert "sim/core: fix Cat bitshift"
This reverts commit 6d6f91a02b.
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2015-10-19 16:08:42 +08:00 |
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Sebastien Bourdeauducq
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6d6f91a02b
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sim/core: fix Cat bitshift
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2015-10-19 16:07:45 +08:00 |
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Sebastien Bourdeauducq
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28962ff438
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sim/core: truncate evaluated values before test in If
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2015-10-19 15:58:21 +08:00 |
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Sebastien Bourdeauducq
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ec80f0fa7e
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build/vivado: quote paths in Tcl (prevents problems with \ on Windows)
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2015-10-19 09:40:44 +08:00 |
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Sebastien Bourdeauducq
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4acb7bc662
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sim: support execution of nested statement lists (typo)
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2015-10-15 13:53:04 +08:00 |
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Sebastien Bourdeauducq
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3b7f1264f1
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sim: support execution of nested statement lists
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2015-10-15 13:52:24 +08:00 |
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Sebastien Bourdeauducq
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48d22a7588
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genlib/fifo: width_or_layout -> width
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2015-10-14 21:36:44 +08:00 |
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Sebastien Bourdeauducq
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8817716d5f
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test/divider: subtests
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2015-10-13 18:39:41 +08:00 |
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Sebastien Bourdeauducq
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e0899c1424
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sim: make sure replaced memory signals are always in VCD signal set
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2015-10-05 12:24:32 +08:00 |
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Sebastien Bourdeauducq
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70e3280579
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travis/conda: build for python 3.5
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2015-10-05 00:25:25 +08:00 |
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Sebastien Bourdeauducq
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b1f8aa2a67
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travis: activate py35
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2015-10-04 23:12:07 +08:00 |
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Sebastien Bourdeauducq
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6258257573
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travis: python 3.5
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2015-10-04 23:08:29 +08:00 |
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Sebastien Bourdeauducq
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6c01f80fc5
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genlib/fifo: add missing imports
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2015-09-30 18:58:46 +08:00 |
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Sebastien Bourdeauducq
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0c1e1c9769
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test/fifo: do not use Record
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2015-09-30 17:06:31 +08:00 |
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Sebastien Bourdeauducq
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4451bb20e5
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genlib/fifo: remove Record support
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2015-09-30 16:39:33 +08:00 |
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Sebastien Bourdeauducq
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913558ab19
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build: stop at the first failed Quartus command
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2015-09-29 15:53:18 +08:00 |
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Sebastien Bourdeauducq
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5e45b6ced6
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build: add missing import for Lattice Diamond
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2015-09-29 15:44:57 +08:00 |
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Sebastien Bourdeauducq
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6d2d70d879
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fhdl/FullMemoryWE: fix clocking
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2015-09-29 13:12:27 +08:00 |
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Sebastien Bourdeauducq
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b4c5ffc1ba
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fhdl: typecheck ClockSignal and ResetSignal arguments
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2015-09-29 13:11:40 +08:00 |
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Sebastien Bourdeauducq
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7c9a7ee757
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build: cleanup
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2015-09-28 20:34:35 +08:00 |
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Sebastien Bourdeauducq
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09003a55e1
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fhdl/specials/Tristate: handle i=None
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2015-09-26 21:49:12 +08:00 |
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Sebastien Bourdeauducq
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e136352e8f
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fhdl/structure: relax type requirements for Array elements
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2015-09-26 21:47:33 +08:00 |
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Sebastien Bourdeauducq
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808cf06add
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fhdl: replace flen with len
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2015-09-26 18:45:10 +08:00 |
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Sebastien Bourdeauducq
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fa1e8cd822
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wrap expressions in Specials
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2015-09-26 16:45:13 +08:00 |
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Sebastien Bourdeauducq
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8f42b6f352
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fhdl: introduce wrap function
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2015-09-26 15:36:28 +08:00 |
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Sebastien Bourdeauducq
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67903494bf
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fhdl: export DUID
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2015-09-26 13:46:57 +08:00 |
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Sebastien Bourdeauducq
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af88a7a3f9
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setup: simpler version check, beta status
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2015-09-24 16:08:39 +08:00 |
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Sebastien Bourdeauducq
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33f344b92a
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fsm: NextState and NextValue should derive from _Statement
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2015-09-23 22:38:10 +08:00 |
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Sebastien Bourdeauducq
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8935ca2c9f
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setup: remove unneeded import
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2015-09-23 09:52:24 +08:00 |
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Sebastien Bourdeauducq
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8421549935
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README.md->rst
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2015-09-23 00:55:37 +08:00 |
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Sebastien Bourdeauducq
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8534562185
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sim: fix slice assign
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2015-09-22 20:33:44 +08:00 |
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Sebastien Bourdeauducq
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88f9d72e74
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conda: use new branch (revert this after merge)
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2015-09-22 17:27:44 +08:00 |
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Sebastien Bourdeauducq
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6005548df6
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setup.py: cleanup
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2015-09-22 17:27:27 +08:00 |
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Sebastien Bourdeauducq
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31ffa8c18f
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fsm: support complex targets in NextValue. Closes #27.
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2015-09-22 16:55:24 +08:00 |
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Sebastien Bourdeauducq
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1857ec6c32
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fhdl/namer: support ClockSignal and ResetSignal. Closes #24
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2015-09-22 14:30:16 +08:00 |
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Sebastien Bourdeauducq
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2c1553fea2
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sim: insert resets, support ClockSignal and ResetSignal
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2015-09-21 22:13:36 +08:00 |
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Sebastien Bourdeauducq
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99af825a5a
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sim: drive clock signals
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2015-09-21 21:53:41 +08:00 |
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Sebastien Bourdeauducq
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a67b4baa0c
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sim: VCD output support
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2015-09-21 21:20:31 +08:00 |
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Sebastien Bourdeauducq
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34ce6b077f
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verilog: remove unneeded import
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2015-09-21 21:19:58 +08:00 |
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Sebastien Bourdeauducq
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b8647a161d
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doc: minor edits
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2015-09-21 21:19:39 +08:00 |
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Sebastien Bourdeauducq
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2ac748aef2
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doc: remove spurious file
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2015-09-20 16:13:08 +08:00 |
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Sebastien Bourdeauducq
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74b0cfc83b
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doc: remove outdated or moved parts, cleanup
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2015-09-20 16:10:40 +08:00 |
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Sebastien Bourdeauducq
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1767eef9cb
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fhdl/visit: support Constant
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2015-09-20 16:10:17 +08:00 |
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Sebastien Bourdeauducq
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87a8531952
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travis: VPI is not there for now
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2015-09-20 15:12:04 +08:00 |
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Sebastien Bourdeauducq
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7f767095ec
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sim: support generators yielding statements
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2015-09-20 15:04:15 +08:00 |
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Sebastien Bourdeauducq
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320dffb4ac
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sim: memory access from generators
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2015-09-20 14:52:26 +08:00 |