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8,681 Commits 40 Branches 14 Tags 51 MiB
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8681 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq eacba52fba transform/unroll: support for variables 2012-10-12 19:54:03 +02:00
Sebastien Bourdeauducq e5fc9cc675 transform: unroll 2012-10-12 13:16:39 +02:00
Sebastien Bourdeauducq ced98d7bee framebuffer: use new SingleGenerator 2012-10-09 21:11:26 +02:00
Sebastien Bourdeauducq d329d40fe9 actorlib/spi: SingleGenerator 2012-10-09 21:11:15 +02:00
Sebastien Bourdeauducq dd6eacba62 Remove uses of the RE signal on field registers 2012-10-09 19:08:37 +02:00
Sebastien Bourdeauducq c473718a12 actorlib/spi/collector: atomic update for write_count 2012-10-09 19:08:09 +02:00
Sebastien Bourdeauducq 85081793cf bank: remove RE signal for field registers 2012-10-09 19:07:53 +02:00
Sebastien Bourdeauducq e410973352 bank: support for atomic writes 2012-10-08 18:43:18 +02:00
Sebastien Bourdeauducq 24877f271b actorlib/spi: fix memory port we/wd 2012-10-04 20:10:24 +02:00
Sebastien Bourdeauducq 035870703f flow/actorlib: Simple Processor Interface (WIP) 2012-10-04 18:22:22 +02:00
Sebastien Bourdeauducq 8101b68965 fhdl: fix instance get_io 2012-09-28 18:02:03 +02:00
Florent Kermarrec f96a28fc32 start MigLa Doc 2012-09-26 23:05:38 +02:00
Sebastien Bourdeauducq c273866b08 fhdl: support expressions in instance ports 2012-09-22 20:51:10 +02:00
Sebastien Bourdeauducq 2fc9cae88a fhdl: support inverted clock ports in instances 2012-09-22 20:50:49 +02:00
Florent Kermarrec 6aeb69b329 update schematics 2012-09-18 23:09:21 +02:00
Florent Kermarrec 7b7ef4f8dc update doc 2012-09-18 16:21:32 +02:00
Florent Kermarrec 4864e08b88 add Setup.py / .gitignore 
start documentation
 2012-09-18 00:22:52 +02:00
Florent Kermarrec b5980a90cc add test_MigLa_1 example : csr access analyzing 2012-09-17 20:15:35 +02:00
Florent Kermarrec 0be7704a85 -add mask on Term 2012-09-17 18:37:23 +02:00
Florent Kermarrec 62bede5eef improve truthtable tool 2012-09-17 17:27:50 +02:00
Florent Kermarrec eba6a2c764 new MigLa Class, simplify & clean up 2012-09-17 17:00:47 +02:00
Florent Kermarrec dbc208395d use of new migen clock_domains convention 2012-09-17 15:27:37 +02:00
Florent Kermarrec a7658cdc6c update README 2012-09-16 11:51:03 +02:00
Florent Kermarrec d97a640b53 add ramp / square / sinus signal generation in examples 2012-09-16 11:49:16 +02:00
Florent Kermarrec 5e84b12980 simplify recorder 2012-09-16 11:48:32 +02:00
Florent Kermarrec d21099f764 examples/de1 : add ramp / square mode 2012-09-15 22:29:50 +02:00
Florent Kermarrec 88d5a593ef fix bug put_ptr on start, separate put / get processes 2012-09-15 20:22:02 +02:00
Florent Kermarrec 50da5bfbf0 remove buggy workaround on read 2012-09-15 20:13:18 +02:00
Florent Kermarrec 84fabd28a2 fixes & clean up 2012-09-15 00:57:52 +02:00
Florent Kermarrec 5b0a8a798f add test_MigLa.py (Wip) 
fixes
 2012-09-14 14:08:20 +02:00
Florent Kermarrec 79af96c190 add access methods 2012-09-14 12:57:09 +02:00
Florent Kermarrec cde176a0b7 migScope/tools/truthtable.py: add function to remove duplicate operands 2012-09-14 12:26:48 +02:00
Florent Kermarrec aac16a9e11 add test_MigIo.py for de0_nano and de1 example 2012-09-13 13:18:03 +02:00
Florent Kermarrec 619671ad73 fix write function 2012-09-13 13:15:05 +02:00
Florent Kermarrec 8e86be1a6a add address parameter to migIo 2012-09-13 13:14:27 +02:00
Florent Kermarrec f4369c917f add spi2Csr tools : Python Host & Arduino Uart<-->Spi bridge 2012-09-13 11:34:19 +02:00
Florent Kermarrec c7e2b0c43e examples/de1: use of MigIo 2012-09-12 22:20:07 +02:00
Florent Kermarrec fc6225273b add MigIo Class 2012-09-12 22:19:42 +02:00
Florent Kermarrec bb6045e279 update README 2012-09-12 18:09:12 +02:00
Florent Kermarrec af64beec53 examples/de1: fix top 2012-09-12 18:07:36 +02:00
Florent Kermarrec fb624fddc4 initialize de1 example 2012-09-12 17:56:36 +02:00
Florent Kermarrec 24b7ba8722 examples/de0_nano : add load cmd / change rst polarity 2012-09-12 16:53:08 +02:00
Sebastien Bourdeauducq 2e14569b5c fhdl/verilog: sort clock domains by name 2012-09-11 10:00:03 +02:00
Sebastien Bourdeauducq 9a18a9df3f fhdl: list signals in execution order 2012-09-11 09:59:37 +02:00
Sebastien Bourdeauducq c86dd3cbef Define clock domains instead of passing extra clocks as regular signals 2012-09-11 00:21:07 +02:00
Sebastien Bourdeauducq 3b3e2f19eb Merge branch 'master' of github.com:milkymist/migen 2012-09-11 00:09:11 +02:00
Sebastien Bourdeauducq 5931c5eb59 Basic support for new clock domain and instance API 2012-09-10 23:47:06 +02:00
Sebastien Bourdeauducq fc3187317b examples: demonstrate multi-clock support 2012-09-10 23:46:19 +02:00
Sebastien Bourdeauducq f7b1e67d08 examples: update LM32 instance 2012-09-10 23:45:27 +02:00
Sebastien Bourdeauducq e16353a281 Multi-clock design support + new instance API 2012-09-10 23:45:02 +02:00