Florent Kermarrec
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2c3e8a2804
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liteeth: fix example design generation and remove VivadoProgrammer from platfom. (TODO: remove others duplicates)
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2015-02-28 11:04:48 +01:00 |
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Florent Kermarrec
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0dfca49e68
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litesata: move file and modify import to misoclib.mem.litesata
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2015-02-28 11:03:24 +01:00 |
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Florent Kermarrec
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b6358be0a1
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merge litesata
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2015-02-28 10:48:08 +01:00 |
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Florent Kermarrec
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df0ba1b03c
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litescope: create example_designs directory
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2015-02-28 10:42:12 +01:00 |
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Florent Kermarrec
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c4ebf244a1
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litescope: move files and modify import to misoclib.tools.litescope
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2015-02-28 10:33:46 +01:00 |
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Florent Kermarrec
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b274e948dc
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merge litescope
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2015-02-28 10:24:49 +01:00 |
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Florent Kermarrec
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a43c555ee3
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misoclib/com: add spi (only SPIMaster for now)
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2015-02-28 09:43:03 +01:00 |
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Florent Kermarrec
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2c51adcd68
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misoclib: better organization (create cores categories: cpu, mem, com, ...)
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2015-02-28 09:40:44 +01:00 |
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Florent Kermarrec
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6b93849a08
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gensoc: parameter check is now more restrictive, add additional info to help user
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2015-02-28 03:12:00 +01:00 |
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Florent Kermarrec
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8e04ef7b95
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test minicon with de0nano (OK) and fix missing self in gensoc
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2015-02-27 20:00:16 +01:00 |
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Florent Kermarrec
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f1200d6388
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gensoc: move I/O for rom initialization to make.py
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2015-02-27 19:48:07 +01:00 |
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Florent Kermarrec
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e07e124118
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sdram: import dfi, lasmibus, wishbone2lasmi from Migen in sdram/bus dir
We will maybe move things, but at least it's in MiSoC now
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2015-02-27 17:07:44 +01:00 |
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Florent Kermarrec
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07b9cabd0d
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gensoc: make it more generic (a SoC does not necessarily have a CPU)
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2015-02-27 16:39:00 +01:00 |
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Florent Kermarrec
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be0eb8d265
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use cachesize reported in wishbone2lasmi
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2015-02-27 14:13:38 +01:00 |
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Florent Kermarrec
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9814001c79
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create cpu dir and move lm32/mor1kx in it
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2015-02-27 10:51:03 +01:00 |
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Florent Kermarrec
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9f636f7985
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move memtest to sdram
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2015-02-27 10:47:54 +01:00 |
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Florent Kermarrec
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b817cf49b3
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replace self._r_register by self._register in all CSR declaration
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2015-02-27 10:36:09 +01:00 |
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Florent Kermarrec
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77a6f580e2
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gensoc: add check_cpu_memory_region and check_csr_region to detect csr and mem regions conflicts
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2015-02-27 10:23:02 +01:00 |
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Florent Kermarrec
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617bc70d7f
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liteeth: move doc
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2015-02-27 09:15:54 +01:00 |
Robert Jordens
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c9ed38dec8
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gensoc: missing self.
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2015-02-26 21:32:11 -07:00 |
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Florent Kermarrec
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09fbbca53e
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gensoc: cpus now directly add their verilog sources
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2015-02-26 20:49:21 +01:00 |
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Florent Kermarrec
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5e8a0c496d
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gensoc: add mem_map and mem_decoder to avoid duplications
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2015-02-26 20:12:27 +01:00 |
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Florent Kermarrec
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5ac5ffe359
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gensoc: get platform_id from platform
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2015-02-26 19:07:19 +01:00 |
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Florent Kermarrec
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02b3f51382
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liteeth: fix example_designs generation
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2015-02-26 10:23:38 +01:00 |
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Florent Kermarrec
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00862a383c
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liteeth: fix import (from liteeth --> from misoclib.liteeth)
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2015-02-26 09:48:37 +01:00 |
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Florent Kermarrec
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60effe1d95
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move files to liteeeth and create example_designs directory
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2015-02-26 09:35:14 +01:00 |
Sebastien Bourdeauducq
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658cb0e405
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merge liteeth
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2015-02-25 10:35:39 -07:00 |
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Sebastien Bourdeauducq
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8015d12692
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move files for misoc integration
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2015-02-25 10:34:11 -07:00 |
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Florent Kermarrec
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0a38b8c74a
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add LiteX external core and remove ethmac
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2015-02-18 10:43:44 -07:00 |
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Florent Kermarrec
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9ebb8f8022
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remove verilog and move mxcrg.v to misoclib/mxcrg
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2015-02-18 10:40:30 -07:00 |
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Florent Kermarrec
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5500c41915
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move lm32/mor1kx submodules to extcores
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2015-02-18 10:39:18 -07:00 |
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Florent Kermarrec
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4c9554b65c
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gensoc: call do_exit after SoC is built
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2015-02-18 10:38:14 -07:00 |
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Florent Kermarrec
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da13bd536e
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gensoc: add csr_data_width and csr_address_width as parameters In some case we want to have mode than 32 CSR or and csr_data_width != 8
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2015-02-14 03:24:23 -08:00 |
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Florent Kermarrec
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9bb7e6d0ab
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ethmac: improve testbenchs
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2014-12-21 17:37:25 +08:00 |
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Sebastien Bourdeauducq
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aac34f011f
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gensoc: support user-defined CSR regions
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2014-11-30 22:29:26 +08:00 |
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Sebastien Bourdeauducq
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8ae3a00a94
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gensoc: simplify WB address decoding
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2014-11-30 22:05:51 +08:00 |
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Sebastien Bourdeauducq
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4189440eef
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minicon: small simplifications
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2014-11-28 08:28:39 +08:00 |
Yann Sionneau
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edb1622668
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spiflash: BB write support
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2014-11-27 23:10:39 +08:00 |
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Sebastien Bourdeauducq
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bab6bb7c4a
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gensoc: fix align
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2014-11-27 23:05:36 +08:00 |
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Sebastien Bourdeauducq
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2cd80990e4
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minicon: fix use of phy phases
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2014-11-27 22:13:17 +08:00 |
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Sebastien Bourdeauducq
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8418ccafdc
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minicon: remove unused signals and fix indent
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2014-11-27 22:12:05 +08:00 |
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Yann Sionneau
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cf92821fcf
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Refactor directory hierarchy of sdram phys and controllers
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2014-11-27 22:09:10 +08:00 |
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Yann Sionneau
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f33b285af1
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Minicon: small SDRAM controller
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2014-11-27 22:09:03 +08:00 |
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Florent Kermarrec
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5202f89db1
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ethmac/last_be: remove fake signal (fixed in Migen)
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2014-11-21 14:48:17 -08:00 |
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Sebastien Bourdeauducq
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b7028848b2
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ethmac: use new EndpointDescription API
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2014-11-20 22:32:32 -08:00 |
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Sebastien Bourdeauducq
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33530e0921
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ethmac: style/renaming
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2014-11-20 18:01:48 -08:00 |
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Florent Kermarec
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603c2641bb
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new Ethernet MAC
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2014-11-20 16:47:22 -08:00 |
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Florent Kermarrec
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8e4b89849c
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use new direct access on endpoints
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2014-10-20 23:13:37 +08:00 |
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Florent Kermarrec
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34ed315a48
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remove trailing whitespaces
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2014-10-17 17:14:40 +08:00 |
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Sebastien Bourdeauducq
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e53fb88b85
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uart: minor cleanup and fix
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2014-10-10 15:33:27 +08:00 |